专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09064892B2 Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same 有权
标题翻译：利用部分掺杂的应力膜部分的半导体器件及其形成方法
公开(公告)号：US09064892B2
公开(公告)日：2015-06-23
申请号：US13221160
申请日：2011-08-30
申请人： Wen Chu Hsiao , Ju Wen Hsiao , Ying Min Chou , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Wen Chu Hsiao , Ju Wen Hsiao , Ying Min Chou , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/165
CPC分类号： H01L29/66636 , H01L21/02529 , H01L21/02532 , H01L21/02535 , H01L21/0262 , H01L21/30604 , H01L29/165 , H01L29/167 , H01L29/7834 , H01L29/7848
摘要： A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.
摘要翻译：半导体结构及其形成方法提供适合用作源极/漏极区域或其它有源器件的高迁移率应力源材料。该结构形成在衬底开口中，并且在上部掺杂有诸如硼的杂质，但是在与开口的表面接触的区域中不含杂质。因此，该结构在高温操作期间抵抗掺杂剂杂质的扩散，并且可以通过使用减压化学气相沉积或减压外延沉积的选择性沉积来形成。

2. 发明申请

US20140007905A1 WAFER CLEANING SYSTEM AND METHOD USING ELECTROLYTIC GAS FOR BACK-END PURGE 审中-公开
标题翻译：用于后端泵的电解气体的清洗系统和方法
公开(公告)号：US20140007905A1
公开(公告)日：2014-01-09
申请号：US13544637
申请日：2012-07-09
申请人： Chung-Ren SUN , Hsiang Hsiang KO , Miao-Cheng LIAO , Wei-Yang TSENG
发明人： Chung-Ren SUN , Hsiang Hsiang KO , Miao-Cheng LIAO , Wei-Yang TSENG
IPC分类号： B08B3/00
CPC分类号： H01L21/67051 , H01L21/67046 , H01L21/68728
摘要： A wafer cleaning system includes a platform, a plurality of wafer holding units over the platform, a front-end rinse nozzle, and a back-end purge unit. The plurality of wafer holding units is set to define a reference plane of wafer holding. The front-end rinse nozzle is above the reference plane and configured to dispense a first rinse fluid toward the reference plane. The back-end purge unit is below the reference plane and configured to dispense an electrolytic gas
摘要翻译：晶片清洁系统包括平台，平台上的多个晶片保持单元，前端冲洗喷嘴和后端清洗单元。多个晶片保持单元被设置为限定晶片保持的参考平面。前端冲洗喷嘴位于参考平面之上，并被配置成朝向参考平面分配第一冲洗流体。后端清洗单元低于参考平面，并配置为分配电解气体

3. 发明申请

US20130256663A1 SURFACE TENSION MODIFICATION USING SILANE WITH HYDROPHOBIC FUNCTIONAL GROUP FOR THIN FILM DEPOSITION 有权
标题翻译：使用硅烷与疏水官能团进行薄膜沉积的表面张力改性
公开(公告)号：US20130256663A1
公开(公告)日：2013-10-03
申请号：US13437209
申请日：2012-04-02
申请人： Lai Wan CHONG , Wen Chu HSIAO , Ying Min CHOU , Hsiang Hsiang KO
发明人： Lai Wan CHONG , Wen Chu HSIAO , Ying Min CHOU , Hsiang Hsiang KO
IPC分类号： H01L21/20 , H01L29/04 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02422 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/78
摘要： A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.
摘要翻译：提供了包括晶体表面和无定形亲水表面的半导体结构。亲水表面用含有疏水官能团的硅烷处理，将亲水表面转化为疏水表面。化学气相沉积或其他合适的沉积方法用于同时在两个表面上沉积材料，并且由于表面处理，沉积的材料在两个表面上表现出优异的附着性。在一个实施例中，该结构是形成在半导体衬底中并由结晶硅表面的至少一部分和非晶氧化硅结构的至少一部分限定的开口。

4. 发明申请

US20130193540A1 Apparatus and Method for Reducing Dark Current in Image Sensors 有权
标题翻译：降低图像传感器暗电流的装置和方法
公开(公告)号：US20130193540A1
公开(公告)日：2013-08-01
申请号：US13436364
申请日：2012-03-30
申请人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
发明人： Miao-Cheng Liao , Jinn-Kwei Liang , Wen-Chieh Hsieh , Shiu-Ko JangJian , Hsiang Hsiang Ko , Ying-Lang Wang
IPC分类号： H01L31/0232 , H01L31/0216
CPC分类号： H01L31/1804 , H01L27/1462 , H01L27/1464 , H01L31/103 , Y02E10/547 , Y02P70/521
摘要： A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
摘要翻译：一种用于减小图像传感器中的暗电流的方法包括提供背面照射的图像传感器晶片，在背面照射的图像传感器晶片的背面上沉积第一钝化层，在第一钝化层上沉积等离子体增强的钝化层并沉积第二钝化层层上的等离子体增强钝化层。

5. 发明申请

US20130069233A1 Reverse Damascene Process 有权
公开(公告)号：US20130069233A1
公开(公告)日：2013-03-21
申请号：US13234299
申请日：2011-09-16
申请人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
发明人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76841 , H01L21/76852 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.

6. 发明授权

US09214393B2 Surface tension modification using silane with hydrophobic functional group for thin film deposition 有权
标题翻译：使用具有疏水官能团的硅烷进行薄膜沉积的表面张力改性
公开(公告)号：US09214393B2
公开(公告)日：2015-12-15
申请号：US13437209
申请日：2012-04-02
申请人： Lai Wan Chong , Wen Chu Hsiao , Ying Min Chou , Hsiang Hsiang Ko
发明人： Lai Wan Chong , Wen Chu Hsiao , Ying Min Chou , Hsiang Hsiang Ko
IPC分类号： H01L21/00 , H01L21/8238 , H01L29/04 , H01L21/02 , H01L29/165 , H01L29/78
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02422 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/78
摘要： A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.
摘要翻译：提供了包括晶体表面和无定形亲水表面的半导体结构。亲水表面用含有疏水官能团的硅烷处理，将亲水表面转化为疏水表面。化学气相沉积或其他合适的沉积方法用于同时在两个表面上沉积材料，并且由于表面处理，沉积的材料在两个表面上表现出优异的附着性。在一个实施例中，该结构是形成在半导体衬底中并由结晶硅表面的至少一部分和非晶氧化硅结构的至少一部分限定的开口。

7. 发明申请

US20140054653A1 TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS 有权
标题翻译：两步骤快速分离（STI）过程
公开(公告)号：US20140054653A1
公开(公告)日：2014-02-27
申请号：US13594254
申请日：2012-08-24
申请人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
发明人： Min Hao Hong , You-Hua Chou , Chih-Tsung Lee , Shiu-Ko JangJian , Miao-Cheng Liao , Hsiang-Hsiang Ko , Chen-Ming Huang
IPC分类号： H01L29/04 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/02538 , H01L21/02609 , H01L21/0334 , H01L21/31053 , H01L21/762 , H01L21/76232 , H01L21/823412 , H01L21/823481 , H01L29/0653 , H01L29/66477 , H01L29/66651 , H01L29/78
摘要： An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
摘要翻译：集成电路器件和用于制造集成电路器件的工艺。集成电路器件包括其中形成有沟槽的衬底，占据沟槽的隔离材料的第一层，在第一隔离材料层上形成的隔离材料的第二层，衬底上的外延生长的硅层，并且水平相邻第二层隔离材料，以及形成在外延生长的硅上的栅极结构，栅极结构限定沟道。

8. 发明申请

US20130295739A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130295739A1
公开(公告)日：2013-11-07
申请号：US13461532
申请日：2012-05-01
申请人： Wen Chu HSIAO , Lai Wan CHONG , Chun-Chieh WANG , Ying Min CHOU , Hsiang Hsiang KO , Ying-Lang WANG
发明人： Wen Chu HSIAO , Lai Wan CHONG , Chun-Chieh WANG , Ying Min CHOU , Hsiang Hsiang KO , Ying-Lang WANG
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L29/0603 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/66515 , H01L29/6653 , H01L29/66636 , H01L29/7845 , H01L29/7847
摘要： In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.
摘要翻译：在制造半导体器件的方法中，在衬底上形成源极/漏极特征。在源极/漏极特征上形成含Si层。在含Si层上形成金属层。金属硅化物层由金属层和含Si层中的Si形成。

9. 发明授权

US08518818B2 Reverse damascene process 有权
标题翻译：反向镶嵌工艺
公开(公告)号：US08518818B2
公开(公告)日：2013-08-27
申请号：US13234299
申请日：2011-09-16
申请人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
发明人： You-Hua Chou , Min Hao Hong , Jian-Shin Tsai , Miao-Cheng Liao , Hsiang Hsiang Ko
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76841 , H01L21/76852 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.
摘要翻译：本公开涉及一种形成后端金属化层的方法。通过在由图案化的光致抗蚀剂层限定的区域内的半导体衬底上形成多个独立金属层结构（即，不被电介质材料包围的金属层结构）来执行该方法。扩散阻挡层以使得扩散阻挡层符合金属层结构的顶部和侧面的方式沉积到金属层结构上。在基板的表面上形成电介质材料以填充金属层结构之间的区域。将衬底平坦化以除去多余的金属和电介质材料并露出金属层结构的顶部。

10. 发明授权

US08497183B2 Devices having a cavity structure and related methods 有权
标题翻译：具有腔结构和相关方法的器件
公开(公告)号：US08497183B2
公开(公告)日：2013-07-30
申请号：US12662681
申请日：2010-04-28
申请人： You-Hua Chou , Hsiang Hsiang Ko , Hung Jui Chang , Yi Ming Chen , Hsien-Wei Lin
发明人： You-Hua Chou , Hsiang Hsiang Ko , Hung Jui Chang , Yi Ming Chen , Hsien-Wei Lin
IPC分类号： H01L21/76
CPC分类号： H01M8/1097 , H01M2008/1095 , Y02P70/56
摘要： A method of making a device. The method comprises providing a first layer including a first material on a surface of a substrate, removing a portion of the first layer and a corresponding portion of the substrate to form an opening in the first layer and a recessed portion in the surface of the substrate, and supplying a liquid mixture to the opening and the recessed portion. The liquid mixture includes a first component having a first chemical affinity to the first material and a second component having a second chemical affinity to the first material, which is smaller than the first chemical affinity. The method also includes removing the second component and forming a second layer including the first component. The second layer covers the recessed portion and adheres to an edge portion of the first layer, such that the second layer and the recessed portion define a cavity.
摘要翻译：制造装置的方法。该方法包括在衬底的表面上提供包括第一材料的第一层，去除第一层的一部分和衬底的对应部分以在第一层中形成开口，并且在衬底的表面中形成凹陷部分并且将液体混合物供应到开口和凹部。液体混合物包括对第一材料具有第一化学亲和力的第一组分和对第一材料具有第二化学亲和力的第二组分，其小于第一化学亲和力。该方法还包括移除第二部件并形成包括第一部件的第二层。第二层覆盖凹部并粘附到第一层的边缘部分，使得第二层和凹部限定一个空腔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式