专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100165749A1 Sense Amplifier Used in the Write Operations of SRAM 有权
标题翻译：读写放大器用于SRAM的写操作
公开(公告)号：US20100165749A1
公开(公告)日：2010-07-01
申请号：US12347140
申请日：2008-12-31
申请人： Jui-Jen Wu , Yi-Tzu Chen
发明人： Jui-Jen Wu , Yi-Tzu Chen
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C7/18 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/413
摘要： A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.
摘要翻译：静态随机存取存储器（SRAM）电路包括一对互补的全局位线和一对互补局部位线。在写入操作中，全局读/写电路耦合到并配置成将小摆动信号写入该对全局位线。 SRAM电路还包括第一多路复用器和第二多路复用器，每个具有第一输入和第二输入。第一多路复用器的第一输入和第二多路复用器的第一输入耦合到该对全局位线中的不同的一个。读出放大器包括耦合到第一多路复用器的输出的第一输入和耦合到第二多路复用器的输出的第二输入。读出放大器被配置为将小摆动信号放大到全摆幅信号，并且在写入操作中将全摆幅信号输出到一对局部位线。

2. 发明授权

US08233330B2 Sense amplifier used in the write operations of SRAM 有权
标题翻译：读写放大器用于SRAM的写操作
公开(公告)号：US08233330B2
公开(公告)日：2012-07-31
申请号：US12347140
申请日：2008-12-31
申请人： Jui-Jen Wu , Yi-Tzu Chen
发明人： Jui-Jen Wu , Yi-Tzu Chen
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/413
摘要： A static random access memory (SRAM) circuit includes a pair of complementary global bit-lines, and a pair of complementary local bit-lines. A global read/write circuit is coupled to, and configured to write a small-swing signal to, the pair of global bit-lines in a write operation. The SRAM circuit further includes a first multiplexer and a second multiplexer, each having a first input and a second input. The first input of the first multiplexer and the first input of the second multiplexer are coupled to different one of the pair of global bit-lines. A sense amplifier includes a first input coupled to an output of the first multiplexer, and a second input coupled to an output of the second multiplexer. The sense amplifier is configured to amplify the small-swing signal to a full-swing signal, and outputs the full-swing signal to the pair of local bit-lines in the write operation.
摘要翻译：静态随机存取存储器（SRAM）电路包括一对互补的全局位线和一对互补局部位线。在写入操作中，全局读/写电路耦合到并配置成将小摆动信号写入该对全局位线。 SRAM电路还包括第一多路复用器和第二多路复用器，每个具有第一输入和第二输入。第一多路复用器的第一输入和第二多路复用器的第一输入耦合到该对全局位线中的不同的一个。读出放大器包括耦合到第一多路复用器的输出的第一输入和耦合到第二多路复用器的输出的第二输入。读出放大器被配置为将小摆动信号放大到全摆幅信号，并且在写入操作中将全摆幅信号输出到一对局部位线。

3. 发明授权

US10632335B2 Magnetically-controlled damping device 有权
公开(公告)号：US10632335B2
公开(公告)日：2020-04-28
申请号：US16037014
申请日：2018-07-17
申请人： Yi-Tzu Chen
发明人： Yi-Tzu Chen
IPC分类号： H02K49/10 , A63B21/005 , F16C1/10 , A63B21/02 , H02K49/04 , A63B21/00 , A63B22/06 , A63B21/04
CPC分类号： A63B21/0056 , A63B21/023 , A63B21/0435 , A63B21/152 , A63B22/0605 , F16C1/10 , H02K49/043
摘要： A magnetically-controlled damping device has a fixing disk, a rotating disk, a plurality of friction-proof sleeves, a plurality of brake shoes, a plurality of magnets, an elastic element, and an operating element. The rotating disk has a plurality of guiding rods sleeved by the friction-proof sleeves respectively. By adjusting a distance between the magnets and a rotating wheel, a damping value of the magnetically-controlled damping device can be adjusted. Moreover, since the friction-proof sleeves are between the guiding rods and the guiding grooves, the guiding rods do not wear out. The magnetically-controlled damping device can provide a more stable damping value and a longer service life.

4. 发明授权

US09295874B1 Elliptical trainer 有权
标题翻译：椭圆教练
公开(公告)号：US09295874B1
公开(公告)日：2016-03-29
申请号：US14551700
申请日：2014-11-24
申请人： Yi-Tzu Chen
发明人： Yi-Tzu Chen
IPC分类号： A63B22/04 , A63B22/00 , A63B69/18 , A63B22/06 , A63B21/015
CPC分类号： A63B22/0664 , A63B21/005 , A63B21/015 , A63B21/225 , A63B22/001 , A63B22/0023 , A63B22/205 , A63B24/0087 , A63B2022/0676 , A63B2022/0682
摘要： An elliptical trainer has a base, two sliding assemblies, a slope adjusting mechanism, and two stride adjusting mechanisms. A transverse diameter of an elliptical path that a user exercises along can be adjusted by driving the slope adjusting mechanism, so as to adjust each stride of the user. A slope of the elliptical path can also be adjusted by driving the stride adjusting mechanisms, so as to provide climbing exercise effects. The elliptical trainer can be easily adjusted to form different exercise modes and intensities. The user's desire for exercising on the elliptical trainer can be increased accordingly.
摘要翻译：椭圆训练机具有底座，两个滑动组件，斜坡调节机构和两个步幅调节机构。用户行使的椭圆形路径的横向直径可以通过驱动斜面调节机构来调整，以便调整用户的每一步。也可以通过驱动步幅调整机构来调整椭圆路径的斜率，以提供攀爬运动效果。椭圆教练可以轻松调整，形成不同的运动模式和强度。可以相应地增加用户对椭圆训练器的锻炼欲望。

5. 发明授权

US08556780B2 Multi-functional linked fitness equipment 失效
标题翻译：多功能连接健身器材
公开(公告)号：US08556780B2
公开(公告)日：2013-10-15
申请号：US13078594
申请日：2011-04-01
申请人： Yi-Tzu Chen
发明人： Yi-Tzu Chen
IPC分类号： A63B21/00
CPC分类号： A63B21/023 , A63B21/00072 , A63B21/0421 , A63B21/055 , A63B21/4015 , A63B21/4033 , A63B21/4047 , A63B22/14 , A63B23/0227 , A63B23/0233 , A63B2208/0238
摘要： A multifunctional linked fitness equipment has an elongated bottom, a seat stand, a front support frame seat pivotally mounted on a front end of the elongated bottom, a rear support frame seat pivotally mounted on a rear end of the seat stand, a link pivotally mounted between the front support frame seat and the rear support frame seat, a front support frame pivotally mounted on the elongated bottom and the front support frame seat, a rear support frame pivotally mounted on the elongated bottom and the rear support frame seat, and at least one resilient member mounted between the rear support frame seat and the elongated bottom. By combining or detaching the front support frame, the rear support frame or the seat stand with or from positioning pins, the fitness equipment can be utilized to selectively exercise the abdominal muscles and the legs based on the users' demand.
摘要翻译：一种多功能连接健身器材具有细长的底部，座椅支架，可枢转地安装在细长底部的前端上的前支撑框架座椅，可枢转地安装在座椅支架的后端上的后支撑框架座，可枢转地安装的连杆在前支撑框架座和后支撑框架座之间，可枢转地安装在细长底部上的前支撑框架和前支撑框架座，可枢转地安装在细长底部和后支撑框架座上的后支撑框架，并且至少安装在后支撑框架座和细长底部之间的一个弹性构件。通过将前支撑框架，后支撑框架或座椅支架与定位销组合或分离，健身器材可以用于根据用户的需求选择性地锻炼腹肌和腿部。

6. 发明申请

US20120023388A1 Parity Look-Ahead Scheme for Tag Cache Memory 有权
标题翻译：标签缓存内存的奇偶性前瞻方案
公开(公告)号：US20120023388A1
公开(公告)日：2012-01-26
申请号：US12842676
申请日：2010-07-23
申请人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： G06F11/10
CPC分类号： G06F12/0875 , G06F11/1064 , H03M13/098
摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
摘要翻译：一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

7. 发明授权

US10632339B2 Treadmill 有权
公开(公告)号：US10632339B2
公开(公告)日：2020-04-28
申请号：US15952295
申请日：2018-04-13
申请人： Yi-Tzu Chen
发明人： Yi-Tzu Chen
IPC分类号： A63B22/00 , A63B22/20 , A63B22/02 , A63B21/012
CPC分类号： A63B22/0046 , A63B21/0125 , A63B22/02 , A63B22/20
摘要： A treadmill includes a base frame, a treadmill belt, a plurality of bearing wheels, a bearing frame, and a limiting frame. The treadmill belt is rotatably installed on the base frame. The bearing wheel is mounted on an inner surface of the treadmill belt. Each bearing wheel is inclined with respect to a horizontal plane, and the bearing frame and the limiting frame are both mounted on the base frame. The bearing frame supports the bearing wheels of the upper section of the treadmill belt. The limiting frame is disposed on one side of the bearing wheel and abuts the bearing wheel. The treadmill has the advantages that the friction between the limiting frame and the bearing wheels can be reduced and can avoid sudden stop or sticking.

8. 发明授权

US09275721B2 Split bit line architecture circuits and methods for memory devices 有权
标题翻译：分离位线架构电路和存储器件的方法
公开(公告)号：US09275721B2
公开(公告)日：2016-03-01
申请号：US12847647
申请日：2010-07-30
申请人： Yi-Tzu Chen , Bin-Hau Lo , Tsai-Hsin Lai , Pey-Huey Chen , Hau-Tai Shieh
发明人： Yi-Tzu Chen , Bin-Hau Lo , Tsai-Hsin Lai , Pey-Huey Chen , Hau-Tai Shieh
IPC分类号： G11C11/40 , G11C11/4097 , G11C5/06
CPC分类号： G11C11/4097 , G11C5/063
摘要： Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.
摘要翻译：公开了用于提供具有缩短的读取访问时间的高密度存储器阵列的装置和方法。多个分割位线沿着相邻存储器位单元的列排列。多输入读出放大器耦合到多个分割位线。多分割位线上的负载减小，并且存储器阵列的相应读取速度比现有技术增强。读出放大器和存储器单元具有公共单元间距布局高度，从而由于使用多个分割位线和读出放大器而不会产生硅面积损失。提高内存阵列效率。

9. 发明授权

US08840529B2 Adjustable elliptical trainer 有权
标题翻译：可调式椭圆训练机
公开(公告)号：US08840529B2
公开(公告)日：2014-09-23
申请号：US13420005
申请日：2012-03-14
申请人： Yi-Tzu Chen
发明人： Yi-Tzu Chen
IPC分类号： A63B22/04 , A63B22/00
CPC分类号： A63B22/001 , A63B22/0015 , A63B22/0664 , A63B2022/0676
摘要： An adjustable elliptical trainer has a base, two driving brackets, two handles, two pedal assemblies and an adjustment assembly. The base has a transmission wheel mounted rotatably thereon. The driving brackets are connected respectively to the transmission wheel. The handles are connected pivotally and respectively to the driving brackets. The pedal assemblies are mounted at opposite sides of the transmission wheels. The adjustment assembly is mounted on the front end of the base and has two guiding rods and a guiding bracket. The guiding rods are mounted on the base. The guiding bracket is connected to the transmission wheel and mounted slidably on the guiding rods. The adjustment assembly allows the pedal assemblies to move along two different elliptical motion paths.
摘要翻译：一个可调节的椭圆训练器有一个底座，两个驱动支架，两个把手，两个踏板组件和一个调整组件。基座具有可旋转地安装在其上的传动轮。驱动支架分别连接到传动轮。把手分别连接到驱动支架上。踏板组件安装在传动轮的相对侧。调节组件安装在基座的前端，并具有两个引导杆和导向支架。引导杆安装在基座上。引导支架连接到传动轮并可滑动地安装在导杆上。调节组件允许踏板组件沿着两个不同的椭圆运动路径移动。

10. 发明授权

US08750053B2 SRAM multiplexing apparatus 有权
标题翻译： SRAM多路复用装置
公开(公告)号：US08750053B2
公开(公告)日：2014-06-10
申请号：US13157163
申请日：2011-06-09
申请人： Yi-Tzu Chen , Wei-jer Hsieh , Tsai-Hsin Lai , Ling-Fang Hsu , Hau-Tai Shieh
发明人： Yi-Tzu Chen , Wei-jer Hsieh , Tsai-Hsin Lai , Ling-Fang Hsu , Hau-Tai Shieh
IPC分类号： G11C7/00
CPC分类号： G11C11/418 , G11C7/1012 , G11C7/18 , G11C11/413
摘要： An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.
摘要翻译： SRAM多路复用装置包括多个本地多路复用器和全局多路复用器。每个本地多路复用器耦合到存储体。全局多路复用器具有多个输入，每个输入耦合到多个本地多路复用器的相应输出端。响应于读操作中的解码地址，本地多路复用器的输入被转发到全局多路复用器的相应输入端。类似地，解码的地址允许全局多路复用器经由缓冲器将输入信号转发到数据输出端口。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式