专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08575965B2 Internal clock gating apparatus 有权
标题翻译：内部时钟选通装置
公开(公告)号：US08575965B2
公开(公告)日：2013-11-05
申请号：US13118060
申请日：2011-05-27
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
IPC分类号： H03K19/096
CPC分类号： G06F1/3287 , G06F1/3237 , Y02D10/128 , Y02D10/171
摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.
摘要翻译：内部时钟选通装置包括静态逻辑块和多米诺逻辑块。静态逻辑块被配置为接收时钟信号和时钟使能信号。多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。

2. 发明申请

US20120299622A1 Internal Clock Gating Apparatus 有权
标题翻译：内部时钟门控器
公开(公告)号：US20120299622A1
公开(公告)日：2012-11-29
申请号：US13118060
申请日：2011-05-27
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yangsyu Lin , Hsiao Wen Lu
IPC分类号： H03K19/096
CPC分类号： G06F1/3287 , G06F1/3237 , Y02D10/128 , Y02D10/171
摘要： An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively.
摘要翻译：内部时钟选通装置包括静态逻辑块和多米诺逻辑块。静态逻辑块被配置为接收时钟信号和时钟使能信号。多米诺骨牌逻辑块被配置为从静态逻辑块的输出接收时钟信号和控制信号。静态逻辑块和多米诺逻辑块进一步被配置为使得当时钟使能信号具有逻辑高状态时，多米诺骨牌逻辑块的输出产生类似时钟信号的相位信号。另一方面，当时钟使能信号具有逻辑低电平状态时，多米诺逻辑块的输出产生逻辑低电平信号。此外，静态逻辑块和多米诺逻辑块可以分别减少内部时钟门控装置的建立时间和延迟时间。

3. 发明申请

US20120098582A1 Flip-Flop Circuit Design 有权
标题翻译：触发器电路设计
公开(公告)号：US20120098582A1
公开(公告)日：2012-04-26
申请号：US12908602
申请日：2010-10-20
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
IPC分类号： H03K3/356 , H03K3/01
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
摘要翻译：触发器电路包括预充电电路，当接收到的时钟信号为低电平时，该充电电路输出高电平信号。当时钟信号为高电平时，延迟时钟输入电路产生与输入信号相同值的延迟时钟输入受控信号。充电保持器电路在接收到充电信号和延迟的时钟输入受控信号时产生一个充电保持信号，当时钟信号为低电平时，该充电信号等于充电信号，并且当时钟信号为高电平时等于延迟的时钟输入受控信号。分离器电路可以接收电荷保持信号和时钟信号并产生反向电荷保持信号。存储电路被配置为接收反转的保持电荷信号，当前状态信号和反相的当前状态信号，并且生成当前状态信号和反相的当前状态信号。

4. 发明申请

US20120023388A1 Parity Look-Ahead Scheme for Tag Cache Memory 有权
标题翻译：标签缓存内存的奇偶性前瞻方案
公开(公告)号：US20120023388A1
公开(公告)日：2012-01-26
申请号：US12842676
申请日：2010-07-23
申请人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： G06F11/10
CPC分类号： G06F12/0875 , G06F11/1064 , H03M13/098
摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
摘要翻译：一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

5. 发明授权

US08416002B2 Flip-flop circuit design 有权
标题翻译：触发电路设计
公开(公告)号：US08416002B2
公开(公告)日：2013-04-09
申请号：US12908602
申请日：2010-10-20
申请人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
发明人： Chi-Lin Liu , Chung-Cheng Chou , Yi-Tzu Chen
IPC分类号： H03K3/356
CPC分类号： H03K3/356121
摘要： A flip-flop circuit includes a precharge circuit that outputs a charge signal high when a received clock signal is LOW. A delay clock input circuit generates a delayed clock input controlled signal with the same value as an input signal when the clock signal is HIGH. A charge keeper circuit, upon receiving the charge signal and the delayed clock input controlled signal, generates a charge keeping signal, which equals the charged signal when the clock signal is LOW and equals the delayed clock input controlled signal when the clock signal is HIGH. A separator circuit can receive the charge keeping signal and clock signal and generate an inverted charge keeping signal. A storage circuit is configured to receive the inverted charge keeping signal, a present state signal, and inverted present state signal, and to generate a present state signal and an inverted present state signal.
摘要翻译：触发器电路包括预充电电路，当接收到的时钟信号为低电平时，该充电电路输出高电平信号。当时钟信号为高电平时，延迟时钟输入电路产生与输入信号相同值的延迟时钟输入受控信号。充电保持器电路在接收到充电信号和延迟的时钟输入受控信号时产生一个充电保持信号，当时钟信号为低电平时，该充电信号等于充电信号，并且当时钟信号为高电平时等于延迟的时钟输入受控信号。分离器电路可以接收电荷保持信号和时钟信号并产生反向电荷保持信号。存储电路被配置为接收反转的保持电荷信号，当前状态信号和反相的当前状态信号，并且生成当前状态信号和反相的当前状态信号。

6. 发明授权

US08359528B2 Parity look-ahead scheme for tag cache memory 有权
标题翻译：标签高速缓冲存储器的奇偶校验方案
公开(公告)号：US08359528B2
公开(公告)日：2013-01-22
申请号：US12842676
申请日：2010-07-23
申请人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
发明人： Chi-Lin Liu , Yi-Tzu Chen , Chung-Cheng Chou
IPC分类号： H03M13/00
CPC分类号： G06F12/0875 , G06F11/1064 , H03M13/098
摘要： A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.
摘要翻译：一种设备包括标签高速缓冲存储器阵列; 配置为接收地址的预奇偶校验单元，以及计算并输出从所述地址的所有位计算的预校验位。比较器被配置为将从标签高速缓冲存储器阵列读取的标签与地址进行比较，并输出读命中位。当标签和地址相同时，读命中位为真，当标签和地址不相同时，读命中位为真。该设备还包括简化的奇偶校验单元，被配置为从标签高速缓冲存储器阵列接收并执行预奇偶校验位，读命中位和奇偶校验位的操作，并输出读取奇偶校验位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式