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1. 发明授权

US06629215B2 Multiple port memory apparatus 失效
标题翻译：多端口存储设备
公开(公告)号：US06629215B2
公开(公告)日：2003-09-30
申请号：US09811916
申请日：2001-03-19
申请人： Juergen Pille , Rolf Sautter , Dieter Wendel , George M. Lattimore
发明人： Juergen Pille , Rolf Sautter , Dieter Wendel , George M. Lattimore
IPC分类号： G06F1200
CPC分类号： G06F9/30141 , G11C7/1006 , G11C7/1012 , G11C7/22 , G11C2207/229 , Y10S707/99953 , Y10S707/99954
摘要： In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.
摘要翻译：为了提供改进的布线管理方法，提出了一种多端口存储装置（200），其包括至少存储有第一存储器阵列（201,202,203）的第一存储器阵列（201）的第一存储器阵列（201,202,203）数据，其中第一存储器字段由第一地址识别，存储第二数据的至少三个存储器阵列（201,202,203）的第二存储器阵列（202）的第一存储器字段，其中第一存储器字段所述第二存储器阵列（202）也由所述第一地址标识，并且所述至少三个存储器阵列（201,202,203）中的第三存储器阵列（203）的第一存储器字段存储选择数据，所述选择数据指示所述第一存储器阵列最后写入数据或第二数据，每个存储在第一地址但不同的存储器阵列中。

2. 发明授权

US06785781B2 Read/write alignment scheme for port reduction of multi-port SRAM cells 失效
标题翻译：用于多端口SRAM单元端口缩减的读/写对准方案
公开(公告)号：US06785781B2
公开(公告)日：2004-08-31
申请号：US09825072
申请日：2001-04-03
申请人： Jens Leenstra , Juergen Pille , Rolf Sautter , Dieter Wendel
发明人： Jens Leenstra , Juergen Pille , Rolf Sautter , Dieter Wendel
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G11C8/16
摘要： A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.
摘要翻译：根据本发明，通过将输入端口的数量和输出端口的数量减少到同时预期的阵列访问的数量n，可以节省相当多的面积。当利用关于阵列利用的一些知识时，可以实现端口的显着减少，从而实现非常相关的区域保存：阵列访问将由最多k个特定组的并发访问执行。一组由多个阵列访问定义，每次访问至多一次访问同一个端口。然后，为了读取，读取结果根据简单的重新布线方案对齐到相应的读取请求者，而对于写入，根据相同或相似的方案在阵列访问之前进行对齐。

3. 发明授权

US07295481B2 Power saving by disabling cyclic bitline precharge 有权
标题翻译：通过禁用循环位线预充电节电
公开(公告)号：US07295481B2
公开(公告)日：2007-11-13
申请号：US10711982
申请日：2004-10-18
申请人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
发明人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C2207/2227
摘要： A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.
摘要翻译：一种访问由位线预充电电路操作的动态硬件存储器块内的存储器单元的方法和系统，其中通过激活补充位线执行差分读/写访问操作。通过确定当前访问操作之后的下一个访问操作是读取还是写入访问，并且仅当读取操作遵循当前访问操作时才执行阵列的位线的预充电来实现功耗的降低。常规的预充电控制信号与指示下一个周期是否为读周期的外部控制信号组合。两个信号的组合可以用作例如简单与门的输入以产生有效的预充电信号。只有当这些位线用于在相应的下一周期中的读取访问时，有效的预充电信号才允许位线预充电。

4. 发明申请

US20130091375A1 Advanced Array Local Clock Buffer Base Block Circuit 审中-公开
标题翻译：高级阵列本地时钟缓冲器基本块电路
公开(公告)号：US20130091375A1
公开(公告)日：2013-04-11
申请号：US13269654
申请日：2011-10-10
申请人： Osama Dengler , Thomas Froehnel , Juergen Pille , Rolf Sautter
发明人： Osama Dengler , Thomas Froehnel , Juergen Pille , Rolf Sautter
IPC分类号： G06F1/04 , G06F17/50
CPC分类号： G06F17/5031 , G06F1/08 , G06F1/10 , G06F17/5045
摘要： A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal.
摘要翻译：提供时钟延伸器机构用于将负有效全局时钟信号的上升沿移动超过反馈路径信号的上升沿。负的有源全局时钟信号和时钟斩波信号被接收在基本块中。第一基块电路修改时钟斩波信号以形成反馈路径信号。第二基块电路使用延迟负有源全局时钟信号将负有源全局时钟信号的上升沿移动到反馈路径信号的上升沿。

5. 发明授权

US07936198B2 Progamable control clock circuit for arrays 有权
标题翻译：阵列控制时钟电路
公开(公告)号：US07936198B2
公开(公告)日：2011-05-03
申请号：US12345758
申请日：2008-12-30
申请人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
发明人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
摘要翻译：可编程时钟控制电路包括：接收斩波块输出的斩波块与基地块之间的基本块，斩波块和脉冲宽度变化块，并向基地块提供脉冲宽度变化输出。脉冲宽度变化块可编程以改变斩波块输出以提供至少三个不同的输出脉冲宽度。该电路还包括一个与基本块的输出相连的时钟延迟块，以延迟输出脉冲并具有时钟信号输出。

6. 发明申请

US20100164586A1 PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS 有权
标题翻译：可编程控制时钟电路
公开(公告)号：US20100164586A1
公开(公告)日：2010-07-01
申请号：US12345758
申请日：2008-12-30
申请人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
发明人： Rolf Sautter , Michael Ju Hyeok Lee , Yuen Hung Chan , Juergen Pille
IPC分类号： H03H11/26
CPC分类号： G06F1/04
摘要： A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
摘要翻译：可编程时钟控制电路包括：接收斩波块输出的斩波块与基地块之间的基本块，斩波块和脉冲宽度变化块，并向基地块提供脉冲宽度变化输出。脉冲宽度变化块可编程以改变斩波块输出以提供至少三个不同的输出脉冲宽度。该电路还包括一个与基本块的输出相连的时钟延迟块，以延迟输出脉冲并具有时钟信号输出。

7. 发明申请

US20090267667A1 Low Power Programmable Clock Delay Generator with Integrated Decode Function 失效
标题翻译：具有集成解码功能的低功耗可编程时钟延迟发生器
公开(公告)号：US20090267667A1
公开(公告)日：2009-10-29
申请号：US12109728
申请日：2008-04-25
申请人： Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
发明人： Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
IPC分类号： H03L7/00
CPC分类号： H03K5/04 , G06F1/10 , H03K5/133 , H03K2005/00058
摘要： A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.
摘要翻译：可编程本地时钟缓冲器在时钟输入和延迟时钟输出之间具有单个反相器。晶体管开关在时钟信号发送状态和非发送状态之间调制单个逆变器级。延迟选择位的组合控制逆变器相对于经由晶体管开关的时钟输入的发送状态的开始和结束的定时。

8. 发明授权

US08237481B2 Low power programmable clock delay generator with integrated decode function 失效
标题翻译：具有集成解码功能的低功耗可编程时钟延迟发生器
公开(公告)号：US08237481B2
公开(公告)日：2012-08-07
申请号：US12109728
申请日：2008-04-25
申请人： Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
发明人： Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
IPC分类号： H03H11/26 , G06F1/04 , H03K17/284
CPC分类号： H03K5/04 , G06F1/10 , H03K5/133 , H03K2005/00058
摘要： A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.
摘要翻译：可编程本地时钟缓冲器在时钟输入和延迟时钟输出之间具有单个反相器。晶体管开关在时钟信号发送状态和非发送状态之间调制单个逆变器级。延迟选择位的组合控制逆变器相对于经由晶体管开关的时钟输入的发送状态的开始和结束的定时。

9. 发明授权

US07813163B2 Single-ended read and differential write scheme 失效
标题翻译：单端读和差分写入方案
公开(公告)号：US07813163B2
公开(公告)日：2010-10-12
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译：提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时，对于写入，选择了传递设备。此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。

10. 发明申请

US20090059688A1 Single-ended read and differential write scheme 失效
标题翻译：单端读和差分写入方案
公开(公告)号：US20090059688A1
公开(公告)日：2009-03-05
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译：提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时，对于写入，选择了传递设备。此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。

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