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1. 发明授权

US06844663B1 Structure and method for forming a multilayer electrode for a flat panel display device 失效
标题翻译：用于形成平板显示装置的多层电极的结构和方法
公开(公告)号：US06844663B1
公开(公告)日：2005-01-18
申请号：US09588115
申请日：2000-05-31
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J9/02 , H01J29/46 , H01J1/02
CPC分类号： H01J9/148 , H01J29/467
摘要： A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.
摘要翻译：多层电极的结构。具体地，在一个实施例中，公开了一种用于平板显示装置的多层电极。多层电极包括金属合金层和保护层。金属合金层包括浓度大于3原子％和6原子％之间的钕。保护层设置在金属合金层上方以形成多层叠层。蚀刻多层堆叠以形成多层电极。

2. 发明授权

US06764366B1 Electrode structure and method for forming electrode structure for a flat panel display 有权
标题翻译：用于形成平板显示器的电极结构的电极结构和方法
公开(公告)号：US06764366B1
公开(公告)日：2004-07-20
申请号：US09999755
申请日：2001-10-31
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J902
CPC分类号： H01J9/148 , H01J29/467
摘要： An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.
摘要翻译：一种用于显示器的电极结构，包括下电极和上电极。在一个实施例中，下电极和上电极由铝合金或银合金形成。在另一个实施例中，上部和下部电极使用沉积有包层的金属合金层形成。使用氮化硅钝化层来保护上电极在后续工艺步骤中不被损坏。还公开了各种其它材料和结构，其保护上电极在后续工艺步骤中不被损坏。

3. 发明授权

US06710525B1 Electrode structure and method for forming electrode structure for a flat panel display 失效
公开(公告)号：US06710525B1
公开(公告)日：2004-03-23
申请号：US09421781
申请日：1999-10-19
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J102
CPC分类号： H01J9/148 , H01J29/467
摘要： An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

4. 发明授权

US06448708B1 Dual-layer metal for flat panel display 失效
标题翻译：双层金属用于平板显示
公开(公告)号：US06448708B1
公开(公告)日：2002-09-10
申请号：US09588118
申请日：2000-05-31
申请人： Kishore K. Chakravorty , Swayambu Ramani , Stephanie J. Oberg , Johan Knall , Duane A. Haven , Ronald S. Besser , Paul J. Louris , Arthur J. Learn , Christopher J. Spindt , Roger W. Barton
发明人： Kishore K. Chakravorty , Swayambu Ramani , Stephanie J. Oberg , Johan Knall , Duane A. Haven , Ronald S. Besser , Paul J. Louris , Arthur J. Learn , Christopher J. Spindt , Roger W. Barton
IPC分类号： H01J102
CPC分类号： H01J9/025 , H01J1/30 , H01J9/148 , H01J2201/30403 , H01J2329/00
摘要： A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a cathodic structure which is formed within an active area on a backplate. The cathodic structure includes a emitter electrode metal composed of strips of aluminum overlain by a layer of cladding material. The use of aluminum and cladding material to form emitter electrode metal gives emitter electrode metal segments which are highly conductive due to the high conductivity of aluminum. By using a suitable cladding material and processing steps, a bond between the aluminum and the cladding material is formed which has good electrical conductivity. In one embodiment, tantalum is used as a cladding material. Tantalum forms a bond with the overlying resistive layer which has good electrical conductivity. Thus, the resulting structure has very high electrical conductivity through the aluminum layer and high conductivity into the resistive layer. Electrode structures that use resistor material, chromium-containing material, nickel and vanadium alloy, and gold are also disclosed.
摘要翻译：平板显示器和平板显示器的形成方法。在一个实施例中，平板显示器包括形成在背板上的有效区域内的阴极结构。阴极结构包括由覆盖材料层覆盖的铝条构成的发射极电极金属。使用铝和包层材料形成发射极电极金属，由于铝的高导电性而导致高导电性的发射极电极金属片段。通过使用合适的覆层材料和加工步骤，形成铝和包层材料之间的结合，其具有良好的导电性。在一个实施例中，钽用作包层材料。钽与具有良好导电性的上覆电阻层形成键。因此，所得结构通过铝层具有非常高的导电性，并且在电阻层中具有高导电性。还公开了使用电阻材料，含铬材料，镍和钒合金以及金的电极结构。

5. 发明授权

US06433473B1 Row electrode anodization 失效
标题翻译：行电极阳极氧化
公开(公告)号：US06433473B1
公开(公告)日：2002-08-13
申请号：US09258021
申请日：1999-02-25
申请人： Kishore K. Chakravorty , Fariborz Nadi , Christopher J. Spindt , Ronald L. Hansen , Colin D. Stanners
发明人： Kishore K. Chakravorty , Fariborz Nadi , Christopher J. Spindt , Ronald L. Hansen , Colin D. Stanners
IPC分类号： H01J162
CPC分类号： H01J9/148 , H01J3/022 , H01J29/02
摘要： A structure and method for forming an column electrode for a field emission display device wherein the column electrode is disposed beneath the field emitters and the row electrode. In one embodiment, the present invention comprises depositing a resistor layer over portions of a column electrode. Next, an inter-metal dielectric layer is deposited over the column electrode. In the present embodiment, the inter-metal dielectric layer is deposited over portions of the resistor layer and over pad areas of the column electrode. After the deposition of the inter-metal dielectric layer, the column electrode is subjected to an anodization process such that exposed regions of the column electrode are anodized. In so doing, the present invention provides a column electrode structure which is resistant to column to row electrode shorts and which is protected from subsequent processing steps.
摘要翻译：一种用于形成用于场发射显示装置的列电极的结构和方法，其中列电极设置在场发射极和行电极之下。在一个实施例中，本发明包括在列电极的部分上沉积电阻层。接下来，在列电极上沉积金属间介电层。在本实施例中，金属间介电层沉积在列电极的电阻层和焊盘区域的部分上。在沉积金属间电介质层之后，对柱电极进行阳极氧化处理，使得阳极氧化柱电极的露出区域。在这样做时，本发明提供了一种对柱对电极短路有抵抗力的列电极结构，并且不受后续处理步骤的保护。

6. 发明授权

US6144144A Patterned resistor suitable for electron-emitting device 失效
标题翻译：图形电阻适用于电子发射器件
公开(公告)号：US6144144A
公开(公告)日：2000-11-07
申请号：US962230
申请日：1997-10-31
申请人： James M. Cleeves , Christopher J. Spindt , Roger W. Barton , Kishore K. Chakravorty , Arthur J. Learn , Stephanie J. Oberg
发明人： James M. Cleeves , Christopher J. Spindt , Roger W. Barton , Kishore K. Chakravorty , Arthur J. Learn , Stephanie J. Oberg
IPC分类号： H01J9/02 , H01J1/304 , H01J3/02 , H01J29/04 , H01J29/46 , H01J31/12 , H01J1/30
CPC分类号： H01J3/021 , H01J1/3042 , H01J29/467 , H01J2201/319 , H01J2329/00
摘要： An electron-emitting device contains a vertical emitter resistor patterned into multiple laterally separated sections (34, 34V, 46, or 46V) situated between the electron-emissive elements (40), on one hand, and emitter electrodes (32), on the other hand. Sections of the resistor are spaced apart along each emitter electrode.
摘要翻译：电子发射器件包含一个垂直发射电阻器，其被图案化成位于电子发射元件（40）和发射极（32）之间的多个横向分开的部分（34,34V，46或46V）上，另一方面。电阻器的部分沿着每个发射极间隔开。

7. 发明授权

US07851109B2 Low stress pellicle frames and reticle pellicle assemblies 有权
标题翻译：低应力防护薄膜框架和标线防护薄膜组件
公开(公告)号：US07851109B2
公开(公告)日：2010-12-14
申请号：US12060220
申请日：2008-03-31
申请人： Kishore K. Chakravorty , Frank E. Abboud , Henry Yun
发明人： Kishore K. Chakravorty , Frank E. Abboud , Henry Yun
IPC分类号： G03F1/00
CPC分类号： G03F1/64 , G03F1/50 , G03F7/70983
摘要： Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.
摘要翻译：低应力标线片防护膜组件。根据本发明的某些实施例，采用减小刚度的防护薄膜框架来减小防护薄膜组件框架在标线板中引起的应力。在其它实施例中，使用减小粘合剂表面的防护薄膜框架来减少防护薄膜组件框架在分划板板中引起的应力。根据其它实施例，采用应力补偿框架来减小包括光罩板，防护薄膜组件和应力补偿框架的组件中的累积应力。

8. 发明授权

US06611419B1 Electronic assembly comprising substrate with embedded capacitors 有权
标题翻译：电子组件包括具有嵌入式电容器的衬底
公开(公告)号：US06611419B1
公开(公告)日：2003-08-26
申请号：US09631037
申请日：2000-07-31
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01G4228
CPC分类号： H01L23/50 , H01L23/49822 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/01078 , H01L2924/09701 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K1/162 , H05K1/185 , H05K3/4611 , H05K3/4629 , H05K3/4688 , H05K2201/0187 , H05K2201/049 , H05K2201/10674 , H05K2201/10734 , H01L2224/05599
摘要： To reduce switching noise, the power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate. In one embodiment, the capacitor is formed of at least one high permittivity layer. In another embodiment, several high permittivity layers are interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.
摘要翻译：为了降低开关噪声，集成电路管芯的电源端子可以耦合到多层陶瓷衬底中的至少一个嵌入式电容器的相应端子。在一个实施例中，电容器由至少一个高电容率层形成。在另一个实施例中，几个高介电常数层与导电层交错。或者，电容器可以包括至少一个嵌入式分立电容器。还描述了电子系统，数据处理系统和各种制造方法。

9. 发明授权

US5436504A Interconnect structures having tantalum/tantalum oxide layers 失效
标题翻译：具有钽/钽氧化物层的互连结构
公开(公告)号：US5436504A
公开(公告)日：1995-07-25
申请号：US64794
申请日：1993-05-19
申请人： Kishore K. Chakravorty , Minas H. Tanielian
发明人： Kishore K. Chakravorty , Minas H. Tanielian
IPC分类号： H01L21/288 , H01L21/48 , H01L21/768 , H05K1/02
CPC分类号： H01L21/76879 , H01L21/288 , H01L21/4846
摘要： A method of fabricating a high-density multilayer copper/polyimide interconnect structure utilizing a blanket tantalum/tantalum oxide layer that electrically connects all of the electroplating seed layers to the edge of the substrate; upon completion of the electroplating process, the excess tantalum/tantalum oxide layer is etched off to produce isolated conductor lines. A multilayer copper/polyimide interconnect structure may be fabricated by repeating this fabrication sequence for each layer.
摘要翻译：一种利用覆盖钽/钽氧化物层的高密度多层铜/聚酰亚胺互连结构的方法，所述覆盖钽/钽氧化物层将所有电镀种子层电连接到衬底的边缘; 在电镀工艺完成后，将多余的钽/钽氧化物层蚀刻掉以产生隔离导体线。多层铜/聚酰亚胺互连结构可以通过重复每个层的这种制造顺序来制造。

10. 发明授权

US5112448A Self-aligned process for fabrication of interconnect structures in semiconductor applications 失效
标题翻译：用于制造半导体应用中的互连结构的自对准工艺
公开(公告)号：US5112448A
公开(公告)日：1992-05-12
申请号：US442238
申请日：1989-11-28
申请人： Kishore K. Chakravorty
发明人： Kishore K. Chakravorty
IPC分类号： H01L21/288 , H01L21/48 , H01L21/768 , H05K3/10 , H05K3/24 , H05K3/46
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/4846 , H01L21/76877 , H05K3/107 , H05K3/243 , H05K3/4644 , Y10S205/917
摘要： A method for fabricating conductors in dielectric trenches in a self-aligned manner. Interconnect modules with a high conductor density are achieved by using a copper-polyimide system as a versatile packaging approach. A photosensitive polyimide is applied to a substrate and lithographically patterned to form polyimide steps having a characteristic positive slope, between which are defined trenches in which the substrate is exposed. A thin electroplating seed layer is deposited over the polyimide steps and the substrate. Copper is electroplated into trenches, but does not plate onto the tops of the polyimide steps, since the electroplating seed layer at that location is not electrically connected to the electroplating seed layer in the bottom of the trenches. The electroplating seed layer on top of the polyimide steps is then removed by chemical etching, plasma machining, or ion-milling. A planar structure is eventually obtained without the use of multiple coatings of polyimide layers or any additional masking layers or lift-off layers.
摘要翻译：一种以自对准方式在介质沟槽中制造导体的方法。具有高导体密度的互连模块通过使用铜 - 聚酰亚胺系统作为通用封装方法来实现。将感光性聚酰亚胺涂布在基板上并进行光刻图案化以形成具有特征正斜率的聚酰亚胺步骤，在其间形成有暴露基板的界定的沟槽。在聚酰亚胺步骤和基底上沉积薄的电镀种子层。由于在该位置处的电镀种子层不与沟槽底部的电镀种子层电连接，所以将铜电镀到沟槽中，但不会沉积在聚酰亚胺步骤的顶部上。然后通过化学蚀刻，等离子体加工或离子研磨去除聚酰亚胺步骤顶部的电镀种子层。最终获得平面结构，而不使用多层聚酰亚胺层或任何附加掩模层或剥离层。

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