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1. 发明授权

US07245000B2 Electrically isolated pillars in active devices 有权
标题翻译：有源器件中电隔离柱
公开(公告)号：US07245000B2
公开(公告)日：2007-07-17
申请号：US10681504
申请日：2003-10-07
申请人： Michael A. Vyvoda , Manish Bhatia , James M. Cleeves , N. Johan Knall
发明人： Michael A. Vyvoda , Manish Bhatia , James M. Cleeves , N. Johan Knall
IPC分类号： H01L27/103
CPC分类号： H01L27/1021
摘要： A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.
摘要翻译：描述了单片三维存储器阵列。存储器阵列包括第一组条带，包括第一端子; 第二组条带，包括第二端子; 第三组条带，包括第三端子; 具有至少一个具有稍微正斜率的侧壁的第一柱，所述柱设置在所述第一和第二组条之间并连接所述第一和第二组条，并且包括第一P掺杂硅区，第一N掺杂硅区和第一绝缘区; 具有至少一个具有稍微正斜率的侧壁的第二柱，所述柱设置在所述第二和第三组条之间并连接所述第二和第三组条，并包括第二P掺杂硅区，第二N掺杂硅区和第二绝缘区; 其中每个支柱基本上没有桁条。

2. 发明授权

US06844663B1 Structure and method for forming a multilayer electrode for a flat panel display device 失效
标题翻译：用于形成平板显示装置的多层电极的结构和方法
公开(公告)号：US06844663B1
公开(公告)日：2005-01-18
申请号：US09588115
申请日：2000-05-31
申请人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
发明人： Jueng Gil Lee , Christopher J. Spindt , Johan Knall , Matthew A. Bonn , Kishore K. Chakravorty
IPC分类号： H01J9/02 , H01J29/46 , H01J1/02
CPC分类号： H01J9/148 , H01J29/467
摘要： A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.
摘要翻译：多层电极的结构。具体地，在一个实施例中，公开了一种用于平板显示装置的多层电极。多层电极包括金属合金层和保护层。金属合金层包括浓度大于3原子％和6原子％之间的钕。保护层设置在金属合金层上方以形成多层叠层。蚀刻多层堆叠以形成多层电极。

3. 发明授权

US06822903B2 Apparatus and method for disturb-free programming of passive element memory cells 有权
标题翻译：无源元件存储单元无干扰编程的装置和方法
公开(公告)号：US06822903B2
公开(公告)日：2004-11-23
申请号：US10403488
申请日：2003-03-31
申请人： Roy E. Scheuerlein , N. Johan Knall
发明人： Roy E. Scheuerlein , N. Johan Knall
IPC分类号： G11C1134
CPC分类号： G11C13/0014 , B82Y10/00 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/72
摘要： In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
摘要翻译：在无源元件存储器阵列中，例如沿着阵列线中的一个或两个具有连续半导体区域的轨道堆叠阵列，对存储器单元的编程可能由于沿着阵列线从所选择的单元的泄漏路径而扰乱附近的存储器单元到相邻的单元格。即使电压不变，也可以通过改变施加到所选择的存储单元的阵列线的编程脉冲的相对定时来大大减小该效果。在示例性三维反熔丝存储器阵列中，施加到存储单元的阳极区域的正向编程脉冲优选地被定时在更轻掺杂的阴极区域被脉冲为低的时间内。

4. 发明授权

US06780683B2 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠，现场可编程，非易失性存储器和制造方法
公开(公告)号：US06780683B2
公开(公告)日：2004-08-24
申请号：US10313763
申请日：2002-12-06
申请人： Mark G. Johnson , James M. Cleeves , Johan Knall
发明人： Mark G. Johnson , James M. Cleeves , Johan Knall
IPC分类号： H01L2182
CPC分类号： G11C17/16
摘要： A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
摘要翻译：三维现场可编程的非易失性存储器包括多层第一和第二交叉导体。支柱在相邻的第一和第二交叉导体的交叉处自对准，并且每个柱包括至少一个抗熔合层。支柱与相邻的导体形成存储器单元，并且每个存储单元包括由反熔丝层分离的第一和第二二极管部件。仅在反熔丝层中断之后，二极管组件才形成二极管。

5. 发明授权

US06777773B2 Memory cell with antifuse layer formed at diode junction 有权
标题翻译：具有反熔丝层的存储单元形成在二极管结
公开(公告)号：US06777773B2
公开(公告)日：2004-08-17
申请号：US10186359
申请日：2002-06-27
申请人： N. Johan Knall
发明人： N. Johan Knall
IPC分类号： H01L2900
CPC分类号： G11C17/16 , H01L27/0688 , H01L27/101
摘要： A memory cell for a three-dimensional intergrated circuit memory is disclosed. The cell includes a very highly doped semiconductor regions with a doping level of 1020 atoms cm−3 or higher. An antifuse region is disposed between the heavily doped region and a more lightly doped region.
摘要翻译：公开了一种用于三维集成电路存储器的存储单元。该电池包括掺杂水平为10 <20> cm -3以上的非常高掺杂的半导体区域。反掺杂区域设置在重掺杂区域和更轻掺杂区域之间。

6. 发明授权

US06631085B2 Three-dimensional memory array incorporating serial chain diode stack 失效
标题翻译：串联链二极管堆叠的三维存储阵列
公开(公告)号：US06631085B2
公开(公告)日：2003-10-07
申请号：US09897705
申请日：2001-06-29
申请人： Bendik Kleveland , Roy E. Scheuerlein , N. Johan Knall , Mark G. Johnson , Thomas H. Lee
发明人： Bendik Kleveland , Roy E. Scheuerlein , N. Johan Knall , Mark G. Johnson , Thomas H. Lee
IPC分类号： G11C1136
CPC分类号： B82Y10/00 , G11C5/025 , G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0014 , G11C13/0028 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2207/063 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021
摘要： A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
摘要翻译：三维存储器阵列包括在数个级中的每一层上的多个轨道堆叠，形成用于阵列的X线和Y线的交替电平。存储单元形成在每条X线和Y线的交点处。每个存储器平面的存储单元都相对于衬底在相同的方向上取向，形成串联链二极管叠层。在某些实施例中，用于阵列的行和列电路被布置为根据所选择的存储器平面中的存储器单元的方向性来交换功能。 X线和Y线的高电压驱动器都能够根据所选存储单元的方向在任一方向上传递写入电流。优选的偏置布置反向仅偏离所选择的存储器平面内的未选择的存储器单元，总共大约N 2个存储器单元，而不是像现有的阵列那样大约3N 2个存储器单元。

7. 发明授权

US6027632A Multi-step removal of excess emitter material in fabricating electron-emitting device 失效
标题翻译：在制造电子发射器件时多步去除过量的发射极材料
公开(公告)号：US6027632A
公开(公告)日：2000-02-22
申请号：US904967
申请日：1997-07-30
申请人： N. Johan Knall , Duane A. Haven , Roger W. Barton , William H. Creel , Christopher J. Spindt
发明人： N. Johan Knall , Duane A. Haven , Roger W. Barton , William H. Creel , Christopher J. Spindt
IPC分类号： B81C1/00 , C25F3/14 , H01J9/02 , C25F3/02
CPC分类号： H01J9/025
摘要： Excess emitter material (52B) is removed in multiple steps during the fabrication of an electron-emitting device. A structure is initially provided in which a dielectric layer (44) overlies a non-insulating region (42), control electrodes (80 or 46/80) overlie the dielectric layer, openings (48/50) extend through the control electrodes and dielectric layer, electron-emissive elements (52A) formed with emitter material are situated in the openings, and an excess layer (52B) of the emitter material overlies the control electrodes and the dielectric layer. Portions of the excess emitter material overlying the dielectric layer in the spaces between the control electrodes are initially removed, preferably with etchant that directly attacks the emitter material. Portions (52C) of the excess emitter material overlying the control electrodes above the electron-emissive elements are subsequently removed to expose the electron-emissive elements.
摘要翻译：在制造电子发射器件期间，多个发射极材料（52B）被多个步骤去除。首先提供一种结构，其中介电层（44）覆盖在非绝缘区域（42）上，控制电极（80或46/80）覆盖在电介质层上，开口（48/50）延伸穿过控制电极和电介质由发射体材料形成的层，电子发射元件（52A）位于开口中，发射极材料的过剩层（52B）覆盖在控制电极和电介质层上。最初除去在控制电极之间的空间中覆盖电介质层的多余发射体材料的部分，最好用直接攻击发射极材料的蚀刻剂。随后去除覆盖电子发射元件上方的控制电极的过量发射体材料的部分（52℃）以露出电子发射元件。

8. 发明授权

US6013986A Electron-emitting device having multi-layer resistor 失效
标题翻译：具有多层电阻器的电子发射器件
公开(公告)号：US6013986A
公开(公告)日：2000-01-11
申请号：US884702
申请日：1997-06-30
申请人： N. Johan Knall , Duane A. Haven , Swayambu Ramani
发明人： N. Johan Knall , Duane A. Haven , Swayambu Ramani
IPC分类号： H01J9/02 , H01J1/304 , H01J3/02 , H01J29/04 , H01J31/12 , H01J63/04
CPC分类号： H01J3/022 , H01J2201/319 , H01J2329/00
摘要： An electron-emitting device employs a multi-layer resistor (46). A lower layer (48) of the resistor overlies an emitter electrode (42). A set of electron-emissive elements (54) overlie an upper layer (50) of the resistor. Each resistive layer extends continuously from a location below each electron-emissive element to a location below each other electron-emissive element. The two resistive layers are of different chemical composition. The upper resistive layer is typically formed with cermet. The lower resistive layer is typically formed with a silicon-carbon compound.
摘要翻译：电子发射器件采用多层电阻（46）。电阻器的下层（48）覆盖发射电极（42）。一组电子发射元件（54）覆盖电阻器的上层（50）。每个电阻层从每个电子发射元件下方的位置连续延伸到彼此电子发射元件下方的位置。两个电阻层的化学成分不同。上电阻层通常由金属陶瓷形成。下电阻层通常由硅 - 碳化合物形成。

9. 发明授权

US6010383A Protection of electron-emissive elements prior to removing excess emitter material during fabrication of electron-emitting device 失效
标题翻译：在制造电子发射器件期间除去多余发射体材料之前，保护电子发射元件
公开(公告)号：US6010383A
公开(公告)日：2000-01-04
申请号：US962525
申请日：1997-10-31
申请人： N. Johan Knall
发明人： N. Johan Knall
IPC分类号： H01J9/02
CPC分类号： H01J9/025
摘要： In a partially finished electron-emitting device having electron-emissive elements (56A) formed at least partially with electrically non-insulating emitter material, electron-emissive element contamination that could result from passage of contaminant material through an excess layer (56B) of the emitter material is inhibited by forming a protective layer (58 or 70) over the excess emitter-material layer before performing additional processing operations on the electron-emitting device. Subsequent to these processing operations, material of the excess and protective layers overlying the electron-emissive elements is removed to expose the electron-emissive elements.
摘要翻译：在具有至少部分地形成有非绝缘发射极材料的电子发射元件（56A）的部分完成的电子发射器件中，可能由污染物质通过过量层（56B）而导致的电子发射元件污染在对电子发射器件执行额外的处理操作之前，通过在过量的发射极 - 材料层上形成保护层（58或70）来抑制发射极材料。在这些处理操作之后，除去覆盖电子发射元件的过量和保护层的材料以暴露电子发射元件。

10. 发明授权

US06954394B2 Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions 有权
标题翻译：用于选择一组存储单元层相关或依赖于温度的操作条件的集成电路和方法
公开(公告)号：US06954394B2
公开(公告)日：2005-10-11
申请号：US10307270
申请日：2002-11-27
申请人： N. Johan Knall , Roy E. Scheuerlein , James M. Cleeves , Bendik Kleveland , Mark G. Johnson
发明人： N. Johan Knall , Roy E. Scheuerlein , James M. Cleeves , Bendik Kleveland , Mark G. Johnson
IPC分类号： G11C7/10 , G11C7/18 , G11C7/22 , G11C29/50 , G11C7/04 , G11C5/06
CPC分类号： G11C29/028 , G11C7/04 , G11C7/1045 , G11C7/18 , G11C7/22 , G11C29/50 , G11C29/50012 , G11C2029/5002 , G11C2207/2281 , G11C2207/229
摘要： The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例涉及用于选择一组存储单元层相关或依赖于温度的操作条件的集成电路和方法。在一个优选实施例中，提供一种存储器阵列，其包括布置在单个集成电路中彼此垂直堆叠的L层的多个存储单元。选择存储器阵列中的存储器单元层，并且基于所选择的存储器来选择N组存储器单元层相关写入条件和/或K组存储器单元层相关读取条件中的一个细胞层。在另一个优选实施例中，测量集成电路的温度，并且基于测量的温度选择一组写入条件和/或一组读取条件。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

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