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1. 发明授权

US5632025A Method for preventing multi-level cache system deadlock in a multi-processor system 失效
标题翻译：防止多处理器系统中多级缓存系统死锁的方法
公开(公告)号：US5632025A
公开(公告)日：1997-05-20
申请号：US696788
申请日：1996-08-14
申请人： Joseph P. Bratt , John Brennan , Peter Y. T. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavaglia
发明人： Joseph P. Bratt , John Brennan , Peter Y. T. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavaglia
IPC分类号： G06F12/08 , G06F12/14
CPC分类号： G06F12/0811
摘要： A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.
摘要翻译：一种用于在多处理器系统中的多级缓存中执行强制原子指令时由于需要数据排他性而防止死锁的方法。系统确定其中诸如整数存储操作的强制原子指令的数据在第一级高速缓存中是否排他的对齐的多字节字。如果是这样，则强制原子指令被允许进入第二级高速缓存流水线。如果不是，则强制原子指令被阻止进入第二级高速缓存流水线并且启动高速缓存未命中和填充操作以使对齐的字在第一级高速缓存中是排他的。

2. 发明授权

US5572704A System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes 失效
标题翻译：用于控制多处理器系统中的分级缓存的系统和方法，包括数据丢失和死锁预防方案
公开(公告)号：US5572704A
公开(公告)日：1996-11-05
申请号：US167005
申请日：1993-12-15
申请人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavagia
发明人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavagia
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0811
摘要： A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.
摘要翻译：一种用于在多处理器计算机系统中防止数据丢失和死锁的方法，其中所述计算机系统中的至少一个处理器包括分级高速缓存。分级缓存具有可写字节的第一级和可写字的第二级。该方法监视第二级高速缓存以确定强制原子（FA）指令是否在二级高速缓存流水线中。如果FA指令被确定在第二级高速缓存流水线中，则延迟到第二级高速缓存的干预，直到FA指令退出第二级高速缓存流水线。以这种方式，通过执行FA指令不会破坏导致干预的高速缓冲存储器访问指令的操作所写入的数据，从而防止数据丢失。该方法还监视第二级高速缓存流水线以确定可能的未命中（PM）指令是否在第二级高速缓存流水线中。如果确定PM指令处于第二级高速缓存流水线中，则FA指令被阻止进入第二级高速缓存流水线，使得当第二级高速缓存中的指令可能为被拘留以代表其进行干预，从而防止计算机系统的处理单元之间的僵局。

3. 发明授权

US5537538A Debug mode for a superscalar RISC processor 失效
标题翻译：超标量RISC处理器的调试模式
公开(公告)号：US5537538A
公开(公告)日：1996-07-16
申请号：US166969
申请日：1993-12-15
申请人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , Chandra S. Joshi , William A. Huffman , Monica R. Nofal , Paul Rodman , Joseph T. Scanlon , Man K. Tang
发明人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , Chandra S. Joshi , William A. Huffman , Monica R. Nofal , Paul Rodman , Joseph T. Scanlon , Man K. Tang
IPC分类号： D06M13/46 , C11D1/04 , C11D1/62 , C11D1/645 , C11D1/65 , C11D1/72 , C11D1/835 , C11D3/00 , D06M20060101 , D06M13/02 , D06M13/184 , D06M13/188 , D06M13/322 , D06M13/463 , G06F9/38 , G06F11/36 , G06F11/34 , G06F9/30
CPC分类号： G06F11/3664 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.
摘要翻译：处理器系统，可在正常操作模式之间切换，无需精确的浮点异常，以及具有精确浮点异常的调试操作模式。处理器系统包括调度整数和浮点指令的调度，具有用于执行整数指令的多级整数流水线的整数单元，以及具有用于执行浮点指令的多级浮点流水线的浮点单元。系统在正常模式下开始运行，并且在接收到“切换到调试模式”的指令时，处理器切换到调试操作模式，具有精确的例外。在调试模式下，一旦调度了浮点指令，就会阻止所有其他指令被提交，直到系统确定浮点指令是否产生异常。因此，允许系统在不处于正常模式时发出精确异常。

4. 发明授权

US5740402A Conflict resolution in interleaved memory systems with multiple parallel accesses 失效
标题翻译：具有多个并行访问的交错存储器系统中的冲突解决
公开(公告)号：US5740402A
公开(公告)日：1998-04-14
申请号：US487240
申请日：1995-06-13
申请人： Joseph P. Bratt , John Brennen , Peter Y. Hsu , Joseph T. Scanlon , Man Kit Tang , Steven J. Ciavaglia
发明人： Joseph P. Bratt , John Brennen , Peter Y. Hsu , Joseph T. Scanlon , Man Kit Tang , Steven J. Ciavaglia
IPC分类号： G06F12/06 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0851 , G06F12/0607
摘要： A conflict resolution system for interleaved memories in processors capable of issuing multiple independent memory operations per cycle. The conflict resolution system includes an address bellow for temporarily storing memory requests, and cross-connect switches to variously route multiple parallel memory requests to multiple memory banks. A control logic block controls the address bellow and the cross-connect switches to reorder the sequence of memory requests to avoid conflicts. The reordering removes conflicts and increases the occurrence of alternating memory requests that can issue simultaneously.
摘要翻译：用于处理器中的交错存储器的冲突解决系统，其能够在每个周期发出多个独立的存储器操作。冲突解决系统包括用于临时存储存储器请求的地址，以及交叉连接交换机以将多个并行存储器请求不同地路由到多个存储体。控制逻辑块控制下面的地址和交叉连接交换机重新排序存储器请求的顺序以避免冲突。重新排序会消除冲突并增加可同时发出的交替内存请求的发生。

5. 发明授权

US09332239B2 Systems and methods for RGB image processing 有权
标题翻译： RGB图像处理系统和方法
公开(公告)号：US09332239B2
公开(公告)日：2016-05-03
申请号：US13484814
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Steven David Hordley , Joseph P. Bratt
IPC分类号： G06K9/00 , H04N9/64 , G06T5/00 , G06T1/20
CPC分类号： H04N9/646 , G06T1/20 , G06T3/4015 , G06T5/002 , G06T5/009 , G06T5/20 , G06T2207/10024 , H04N5/365 , H04N9/045 , H04N9/735
摘要： Systems and methods for processing image data in RGB format are provided. In one example, an electronic device includes memory to store image data in raw or RGB format, or both, and an RGB image processing pipeline to process the image data. Specifically, the RGB image processing pipeline may process the image data regardless of whether the image data is of raw or RGB format. The RGB image processing pipeline may include receiving logic to receive the image data in raw or RGB format and demosaicing logic to, when the receiving logic receives the image data in raw format, convert the image data into RGB format. The logic may include local tone mapping logic configured to apply spatially varying tone curves to the image data, a color correction matrix configured to correct color in the image data, and gamma logic configured to transform the image data into gamma space.
摘要翻译：提供了以RGB格式处理图像数据的系统和方法。在一个示例中，电子设备包括用于以原始或RGB格式或两者存储图像数据的存储器和用于处理图像数据的RGB图像处理流水线。具体而言，RGB图像处理流水线可以处理图像数据，而不管图像数据是原始还是RGB格式。 RGB图像处理流水线可以包括接收逻辑以接收原始或RGB格式的图像数据和去马赛克逻辑，当接收逻辑以原始格式接收图像数据时，将图像数据转换为RGB格式。逻辑可以包括被配置为将空间变化的色调曲线应用于图像数据的本地色调映射逻辑，配置为校正图像数据中的颜色的色彩校正矩阵，以及被配置为将图像数据变换为伽马空间的伽马逻辑。

6. 发明授权

US08717391B2 User interface pipe scalers with active regions 有权
标题翻译：用户界面管道缩放器与活动区域
公开(公告)号：US08717391B2
公开(公告)日：2014-05-06
申请号：US12950267
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： G09G5/00 , G06F13/00 , G09G5/02
CPC分类号： G09G5/024 , G09G5/022 , G09G5/14 , G09G5/363 , G09G5/397
摘要： A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.
摘要翻译：显示管可以包括提取电路和缩放器单元，并且可以用定义图像帧的有效区域的信息来编程。活动区域内的像素是要显示的活动像素，活动区域之外的像素是不显示的不活动像素。提取电路可以从存储器检索帧，检索有效像素，而不检索由寄存器的编程内容定义的非活动像素。缩放器单元可以从获取的像素产生缩放的像素，将每个缩放的像素基于相应的相应的像素集。当相应的相应像素集合的给定像素是非活动像素时，缩放器单元可以基于相应的相应像素集合中的一个或多个有效像素来分配给定像素的估计值。缩放器单元可以将缩放的像素提供给用于与其他像素混合的混合单元。

7. 发明申请

US20130322746A1 SYSTEMS AND METHODS FOR YCC IMAGE PROCESSING 有权
标题翻译： YCC图像处理系统与方法
公开(公告)号：US20130322746A1
公开(公告)日：2013-12-05
申请号：US13484926
申请日：2012-05-31
申请人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
发明人： Guy Cote , Sheng Lin , Suk Hwan Lim , D. Amnon Silverstein , Simon Wolfenden Butler , Mark A. Zimmer , Joseph P. Bratt
IPC分类号： G06K9/40
CPC分类号： G06T1/20 , G06T3/4015
摘要： Systems and methods for processing YCC image data provided. In one example, an electronic device includes memory to store image data in RGB or YCC format and a YCC image processing pipeline to process the image data. The YCC image processing pipeline may include receiving logic configured to receive the image data in RGB or YCC format and color space conversion logic configured to, when the image data is received in RGB format, convert the image data into YCC format. The YCC image processing logic may also include luma sharpening and chroma suppression logic; brightness, contrast, and color adjustment logic; gamma logic; chroma decimation logic; scaling logic; and chromanoise reduction logic.
摘要翻译：用于处理提供的YCC图像数据的系统和方法。在一个示例中，电子设备包括以RGB或YCC格式存储图像数据的存储器和用于处理图像数据的YCC图像处理流水线。 YCC图像处理流水线可以包括被配置为接收RGB或YCC格式的图像数据的接收逻辑，以及配置为当以RGB格式接收图像数据时将图像数据转换为YCC格式的颜色空间转换逻辑。 YCC图像处理逻辑还可以包括亮度锐化和色度抑制逻辑; 亮度，对比度和颜色调整逻辑; 伽玛逻辑; 色度抽取逻辑; 缩放逻辑; 和色度降低逻辑。

8. 发明申请

US20130322745A1 Local Image Statistics Collection 有权
标题翻译：本地图像统计信息收集
公开(公告)号：US20130322745A1
公开(公告)日：2013-12-05
申请号：US13484741
申请日：2012-05-31
申请人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
发明人： Suk Hwan Lim , D. Amnon Silverstein , Guy Cote , Steven David Hordley , Graham Finlayson , Weichun Ku , Joseph P. Bratt
IPC分类号： G06K9/36
CPC分类号： H04N9/73 , H04N5/142 , H04N9/045 , H04N9/735 , H04N2209/046
摘要： Systems and methods for generating local image statistics are provided. In one example, an image signal processing system may include a statistics pipeline with image processing logic and local image statistics collection logic. The image processing logic may receive and process pixels of raw image data. The local image statistics collection logic may generate a local histogram associated with a luminance of the pixels of a first block of pixels of the raw image data or a thumbnail in which a pixel of the thumbnail represents a downscaled version of the luminance of the pixels of the first block of the pixel. The raw image data may include many other blocks of pixels of the same size as the first block of pixels.
摘要翻译：提供了生成本地图像统计信息的系统和方法。在一个示例中，图像信号处理系统可以包括具有图像处理逻辑和本地图像统计信息收集逻辑的统计流水线。图像处理逻辑可以接收和处理原始图像数据的像素。本地图像统计收集逻辑可以生成与原始图像数据的第一像素块的像素的亮度相关联的局部直方图或缩略图，其中缩略图的像素表示缩略图的像素的亮度像素的第一个块。原始图像数据可以包括与第一像素块相同尺寸的许多其他像素块。

9. 发明授权

US08508612B2 Image signal processor line buffer configuration for processing ram image data 有权
标题翻译：用于处理原始图像数据的图像信号处理器线缓冲器配置
公开(公告)号：US08508612B2
公开(公告)日：2013-08-13
申请号：US12895396
申请日：2010-09-30
申请人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt
发明人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt
IPC分类号： H04N5/228
CPC分类号： H04N9/045 , G06T3/4015
摘要： The present disclosure provides techniques relates to the implementation of a raw pixel processing unit using a set of line buffers. In one embodiment, the set of line buffers may include a first subset and second subset. Various logical units of the raw pixel processing unit may be implemented using the first and second subsets of line buffers in a shared manner. For instance, in one embodiment, defective pixel correction and detection logic may be implemented using the first subset of line buffers. The second subset of line buffers may be used to implement lens shading correction logic, gain, offset, and clamping logic, and demosaicing logic. Further, noise reduction may also be implemented using at least a portion of each of the first and second subsets of line buffers.
摘要翻译：本公开提供了技术涉及使用一组行缓冲器的原始像素处理单元的实现。在一个实施例中，行缓冲器组可以包括第一子集和第二子集。可以以共享的方式使用第一和第二子行的行缓冲器来实现原始像素处理单元的各种逻辑单元。例如，在一个实施例中，可以使用线缓冲器的第一子集来实现有缺陷的像素校正和检测逻辑。行缓冲器的第二子集可用于实现镜头阴影校正逻辑，增益，偏移和钳位逻辑以及去马赛克逻辑。此外，还可以使用行缓冲器的第一和第二子集中的每一个的至少一部分来实现噪声降低。

10. 发明申请

US20120151104A1 PIO INTERJECTION BETWEEN BEATS OF A DMA OPERATION 有权
标题翻译： DMA操作之间的PIO间隔
公开(公告)号：US20120151104A1
公开(公告)日：2012-06-14
申请号：US12966946
申请日：2010-12-13
申请人： Joseph P. Bratt , Lakshmi Rao
发明人： Joseph P. Bratt , Lakshmi Rao
IPC分类号： G06F13/36 , G06F13/28
CPC分类号： G06F13/28
摘要： Techniques are disclosed relating to detecting and interjecting a programmed input/output (PIO) operation into a direct memory access (DMA) operation. In one embodiment, an integrated circuit may include a DMA controller that may contain a control circuit, a DMA unit, and a PIO unit. The control circuit may be configured to detect a pending PIO operation during a DMA operation and interject the PIO operation onto a shared path during the same clock cycle as or the first clock cycle following the detection of the pending PIO operation. The DMA operation may consist of multiple single-clock-cycle beats. In one embodiment, a PIO operation may be interjected onto the shared path between beats of a DMA operation, on consecutive clock cycles. At the next clock cycle following the PIO operation, the control circuit may resume the next beat of the DMA operation.
摘要翻译：公开了关于将编程的输入/输出（PIO）操作检测和插入到直接存储器访问（DMA）操作中的技术。在一个实施例中，集成电路可以包括可以包含控制电路，DMA单元和PIO单元的DMA控制器。控制电路可以被配置为在DMA操作期间检测待处理的PIO操作，并且在与待处理的PIO操作的检测之后的相同时钟周期期间或在第一时钟周期之后将PIO操作插入到共享路径上。 DMA操作可以由多个单时钟周期节拍组成。在一个实施例中，可以在连续的时钟周期上将PIO操作插入在DMA操作的节拍之间的共享路径上。在PIO操作之后的下一个时钟周期，控制电路可以恢复DMA操作的下一个节拍。

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