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1. 发明授权

US5572704A System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes 失效
标题翻译：用于控制多处理器系统中的分级缓存的系统和方法，包括数据丢失和死锁预防方案
公开(公告)号：US5572704A
公开(公告)日：1996-11-05
申请号：US167005
申请日：1993-12-15
申请人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavagia
发明人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavagia
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0811
摘要： A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the second level cache are delayed until the FA instruction exits the second level cache pipeline. In this manner data written by operation of cache memory access instruction that cause the interventions is not destroyed by the execution of the FA instruction, thereby preventing data loss. The method also monitors the second level cache pipeline to determine if a possible miss (PM) instruction is in the second level cache pipeline. If a PM instruction is determined to be in the second level cache pipeline, the FA instructions are prevented from entering the second level cache pipeline such that execution of interventions to the second level cache is not prevented when an instruction in the second level cache may be detained to process an intervention in its behalf, thereby preventing deadlock between processing units of the computer system.
摘要翻译：一种用于在多处理器计算机系统中防止数据丢失和死锁的方法，其中所述计算机系统中的至少一个处理器包括分级高速缓存。分级缓存具有可写字节的第一级和可写字的第二级。该方法监视第二级高速缓存以确定强制原子（FA）指令是否在二级高速缓存流水线中。如果FA指令被确定在第二级高速缓存流水线中，则延迟到第二级高速缓存的干预，直到FA指令退出第二级高速缓存流水线。以这种方式，通过执行FA指令不会破坏导致干预的高速缓冲存储器访问指令的操作所写入的数据，从而防止数据丢失。该方法还监视第二级高速缓存流水线以确定可能的未命中（PM）指令是否在第二级高速缓存流水线中。如果确定PM指令处于第二级高速缓存流水线中，则FA指令被阻止进入第二级高速缓存流水线，使得当第二级高速缓存中的指令可能为被拘留以代表其进行干预，从而防止计算机系统的处理单元之间的僵局。

2. 发明授权

US5537538A Debug mode for a superscalar RISC processor 失效
标题翻译：超标量RISC处理器的调试模式
公开(公告)号：US5537538A
公开(公告)日：1996-07-16
申请号：US166969
申请日：1993-12-15
申请人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , Chandra S. Joshi , William A. Huffman , Monica R. Nofal , Paul Rodman , Joseph T. Scanlon , Man K. Tang
发明人： Joseph P. Bratt , John Brennan , Peter Y. Hsu , Chandra S. Joshi , William A. Huffman , Monica R. Nofal , Paul Rodman , Joseph T. Scanlon , Man K. Tang
IPC分类号： D06M13/46 , C11D1/04 , C11D1/62 , C11D1/645 , C11D1/65 , C11D1/72 , C11D1/835 , C11D3/00 , D06M20060101 , D06M13/02 , D06M13/184 , D06M13/188 , D06M13/322 , D06M13/463 , G06F9/38 , G06F11/36 , G06F11/34 , G06F9/30
CPC分类号： G06F11/3664 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.
摘要翻译：处理器系统，可在正常操作模式之间切换，无需精确的浮点异常，以及具有精确浮点异常的调试操作模式。处理器系统包括调度整数和浮点指令的调度，具有用于执行整数指令的多级整数流水线的整数单元，以及具有用于执行浮点指令的多级浮点流水线的浮点单元。系统在正常模式下开始运行，并且在接收到“切换到调试模式”的指令时，处理器切换到调试操作模式，具有精确的例外。在调试模式下，一旦调度了浮点指令，就会阻止所有其他指令被提交，直到系统确定浮点指令是否产生异常。因此，允许系统在不处于正常模式时发出精确异常。

3. 发明授权

US5632025A Method for preventing multi-level cache system deadlock in a multi-processor system 失效
标题翻译：防止多处理器系统中多级缓存系统死锁的方法
公开(公告)号：US5632025A
公开(公告)日：1997-05-20
申请号：US696788
申请日：1996-08-14
申请人： Joseph P. Bratt , John Brennan , Peter Y. T. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavaglia
发明人： Joseph P. Bratt , John Brennan , Peter Y. T. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavaglia
IPC分类号： G06F12/08 , G06F12/14
CPC分类号： G06F12/0811
摘要： A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.
摘要翻译：一种用于在多处理器系统中的多级缓存中执行强制原子指令时由于需要数据排他性而防止死锁的方法。系统确定其中诸如整数存储操作的强制原子指令的数据在第一级高速缓存中是否排他的对齐的多字节字。如果是这样，则强制原子指令被允许进入第二级高速缓存流水线。如果不是，则强制原子指令被阻止进入第二级高速缓存流水线并且启动高速缓存未命中和填充操作以使对齐的字在第一级高速缓存中是排他的。

4. 发明授权

US5510934A Memory system including local and global caches for storing floating point and integer data 失效
标题翻译：内存系统包括用于存储浮点数和整型数据的本地和全局缓存
公开(公告)号：US5510934A
公开(公告)日：1996-04-23
申请号：US168832
申请日：1993-12-15
申请人： John Brennan , Peter Y. Hsu , William A. Huffman , Paul Rodman , Joseph T. Scanlon , Man K. Tang , Steve J. Ciavaglia
发明人： John Brennan , Peter Y. Hsu , William A. Huffman , Paul Rodman , Joseph T. Scanlon , Man K. Tang , Steve J. Ciavaglia
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0897 , G06F12/0831 , G06F12/0851
摘要： A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and address data for refilling the local cache. Coherence between the local cache and global cache is maintained by writing through to the global cache during integer stores. Local cache words are invalidated when data is written to the global cache during an army processor store.
摘要翻译：用于数据处理器的分级高速缓冲存储器系统包括单个芯片整数单元，诸如浮点单元的陆军处理器，外部主存储器和分割级高速缓存。分级高速缓存包括片上快速本地高速缓存，具有低延迟，用于整数单元用于整数和地址数据的加载和存储，以及用于存储诸如浮点数据的数据阵列的片外流水线全局高速缓存供数组处理器使用，整数和地址数据用于重新填充本地缓存。通过在整数存储期间写入全局缓存来维护本地缓存和全局缓存之间的一致性。在陆军处理器存储期间将数据写入全局缓存时，本地缓存字无效。

5. 发明授权

US08431557B2 Treatment of menopause-associated symptoms 有权
标题翻译：治疗绝经相关症状
公开(公告)号：US08431557B2
公开(公告)日：2013-04-30
申请号：US13408760
申请日：2012-02-29
申请人： John Brennan , Earl E. Sands , Rex Horton , Zurab Bebia
发明人： John Brennan , Earl E. Sands , Rex Horton , Zurab Bebia
IPC分类号： A61K31/565 , A61P15/02 , A61P9/00 , A61P15/00 , A61P5/30 , A61P15/12
CPC分类号： A61K31/565 , A61K9/0014 , A61K9/06 , A61K31/56
摘要： Described are estradiol-containing pharmaceutical compositions and, and methods using the same to alleviate menopause-related symptoms, such as hot flushes, by topically administering estradiol at low effective doses.
摘要翻译：描述的是含雌二醇的药物组合物，以及使用该组合物的方法，通过以低有效剂量局部施用雌二醇来减轻更年期相关症状，例如热潮红。

6. 发明授权

US08281734B2 Web sealing device 失效
标题翻译：网密封装置
公开(公告)号：US08281734B2
公开(公告)日：2012-10-09
申请号：US12299131
申请日：2006-05-02
申请人： John Kennedy , Richard Sibbick , Frank Swallow , Peter Dobbyn , Alan Hynes , John Brennan
发明人： John Kennedy , Richard Sibbick , Frank Swallow , Peter Dobbyn , Alan Hynes , John Brennan
IPC分类号： B05C11/00 , C23C16/50 , B01J19/08 , H05H1/24
CPC分类号： F16J15/168 , D06B23/16
摘要： An apparatus for treating a travelling web of material in a predetermined gaseous atmosphere comprising a chamber (1) through which a moving web of material (2) is transported from an inlet at a first end of the chamber (1) to an outlet at a second end and a means for introducing and controlling gas (5) intended to provide said predetermined gaseous atmosphere within said chamber (1), wherein said inlet and outlet each comprise a sealing means (4a, 4b) designed to enable passage of said web of material (2) therethrough whilst minimising the ingress of an external gas boundary layer (3) around said web of material (2) characterised in that said apparatus also comprises one or more re-circulation channels (7, 8) adapted to re-circulate gases within said chamber (1) from the second end of the chamber to the first end of the chamber thereby negating or substantially negating any pressure difference within the chamber (1) between said inlet and outlet. Said apparatus is preferably s part of a non thermal equilibrium plasma generating apparatus or corona discharge assembly.
摘要翻译：一种用于处理预定气体气氛中的材料的移动网状物的设备，包括腔室（1），材料（2）的移动腹板通过所述腔室从腔室（1）的第一端处的入口输送到腔室第二端和用于引入和控制旨在在所述腔室（1）内提供所述预定气态气体的气体（5）的装置，其中所述入口和出口各自包括密封装置（4a，4b），所述密封装置设计成使所述容器材料（2）穿过其中，同时最小化围绕所述材料网（2）的外部气体边界层（3）的进入，其特征在于，所述装置还包括一个或多个再循环通道（7,8），其适于重新循环所述腔室（1）内的从腔室的第二端到腔室的第一端的气体，从而抵消或基本上否定所述入口和出口之间的腔室（1）内的任何压力差。所述装置优选地是非热平衡等离子体产生装置或电晕放电组件的一部分。

7. 发明授权

US07910710B2 DNA enzymes 有权
标题翻译： DNA酶
公开(公告)号：US07910710B2
公开(公告)日：2011-03-22
申请号：US10504616
申请日：2003-02-11
申请人： Yingfu Li , John Brennan , Shirley Mei , Zhongjie Liu
发明人： Yingfu Li , John Brennan , Shirley Mei , Zhongjie Liu
IPC分类号： C07H21/02
CPC分类号： C12N15/113 , C07K2319/00 , C12N9/22 , C12N2310/12 , C12N2310/3517 , C12Q1/6813 , C12Q2563/107
摘要： Methods for the selection of novel signaling allosteric DNA enzymes are provided. In particular, fluorescent signaling allosteric DNA enzymes are described. The selection system is based on the cleavage of an ribonucleotide flanked by a fluorophore modified nucleotide and a quencher modified oligonucleotide. Both cis-acting and trans-acting allosteric DNA enzymes are identified, as well as aptamer/DNA enzyme conjugates.
摘要翻译：提供了选择新型信号变构DNA酶的方法。特别地，描述了荧光信号变构DNA酶。选择系统基于侧翼为荧光团修饰的核苷酸和淬灭剂修饰的寡核苷酸的核糖核苷酸的切割。鉴定顺式作用和反式作用的变构DNA酶，以及适体/ DNA酶缀合物。

8. 发明申请

US20090282621A1 Web Sealing Device 失效
标题翻译：网页封口机
公开(公告)号：US20090282621A1
公开(公告)日：2009-11-19
申请号：US12299131
申请日：2006-05-02
申请人： John Kennedy , Richard Sibbick , Frank Swallow , Peter Dobbyn , Alan Hynes , John Brennan
发明人： John Kennedy , Richard Sibbick , Frank Swallow , Peter Dobbyn , Alan Hynes , John Brennan
IPC分类号： D06B1/02 , B08B3/00
CPC分类号： F16J15/168 , D06B23/16
摘要： An apparatus for treating a travelling web of material in a predetermined gaseous atmosphere comprising a chamber (1) through which a moving web of material (2) is transported from an inlet at a first end of the chamber (1) to an outlet at a second end and a means for introducing and controlling gas (5) intended to provide said predetermined gaseous atmosphere within said chamber (1), wherein said inlet and outlet each comprise a sealing means (4a, 4b) designed to enable passage of said web of material (2) therethrough whilst minimising the ingress of an external gas boundary layer (3) around said web of material (2) characterised in that said apparatus also comprises one or more re-circulation channels (7, 8) adapted to re-circulate gases within said chamber (1) from the second end of the chamber to the first end of the chamber thereby negating or substantially negating any pressure difference within the chamber (1) between said inlet and outlet. Said apparatus is preferably s part of a non thermal equilibrium plasma generating apparatus or corona discharge assembly.
摘要翻译：一种用于处理预定气体气氛中的材料的移动网状物的设备，包括腔室（1），材料（2）的移动腹板通过所述腔室从腔室（1）的第一端处的入口输送到腔室第二端和用于引入和控制旨在在所述腔室（1）内提供所述预定气态气体的气体（5）的装置，其中所述入口和出口各自包括密封装置（4a，4b），所述密封装置设计成使所述容器材料（2）穿过其中，同时最小化围绕所述材料网（2）的外部气体边界层（3）的进入，其特征在于，所述装置还包括一个或多个再循环通道（7,8），其适于重新循环所述腔室（1）内的从腔室的第二端到腔室的第一端的气体，从而抵消或基本上否定所述入口和出口之间的腔室（1）内的任何压力差。所述装置优选地是非热平衡等离子体产生装置或电晕放电组件的一部分。

9. 发明申请

US20050191793A1 Semiconductor packaging techniques for use with non-ceramic packages 有权
标题翻译：用于非陶瓷封装的半导体封装技术
公开(公告)号：US20050191793A1
公开(公告)日：2005-09-01
申请号：US10788162
申请日：2004-02-26
申请人： John Brennan , Joseph Freund , Curtis Miller , Richard Shanaman
发明人： John Brennan , Joseph Freund , Curtis Miller , Richard Shanaman
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/047 , H01L23/31 , H01L23/433 , H01L23/495
CPC分类号： H01L23/49562 , H01L23/047 , H01L23/315 , H01L23/4334 , H01L23/49568 , H01L24/48 , H01L2224/32188 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/14 , H01L2924/16195 , H01L2924/181 , H01L2224/45099 , H01L2924/00
摘要： A method for attaching at least one IC die to a non-ceramic IC package including a leadframe and a base, the IC package being configured for receiving the at least one IC die, includes attaching the IC die to an upper surface of a thermal carrier in a manner which facilitates thermal transfer between the die and the carrier. The method further includes attaching the thermal carrier having the IC die attached thereto to an upper surface of the base of the IC package. In this manner, one or more IC dies may be attached to a standard plastic IC package without a significant impact on thermal transfer in the device and at a significant cost savings compared to ceramic IC packages.
摘要翻译：一种用于将至少一个IC管芯附接到包括引线框架和基座的非陶瓷IC封装的方法，所述IC封装构造成用于接收所述至少一个IC管芯，包括将所述IC管芯附接到热载体的上表面以促进模具和载体之间的热传递的方式。该方法还包括将具有附接到其中的IC芯片的热载体附接到IC封装的基座的上表面。以这种方式，与陶瓷IC封装相比，可以将一个或多个IC管芯连接到标准塑料IC封装，而不会对器件中的热传递产生显着影响。

10. 外观设计

USD507636S1 Electric aromatherapy diffuser 失效
标题翻译：电动芳香疗法扩散器
公开(公告)号：USD507636S1
公开(公告)日：2005-07-19
申请号：US29198319
申请日：2004-01-27
申请人： David Baraky , John Brennan
设计人： David Baraky , John Brennan

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