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1. 发明授权

US07349223B2 Enhanced compliant probe card systems having improved planarity 失效
标题翻译：增强的兼容性探针卡系统具有改进的平面性
公开(公告)号：US07349223B2
公开(公告)日：2008-03-25
申请号：US10870095
申请日：2004-06-16
申请人： Joseph Michael Haemer , Fu Chiung Chong , Douglas N. Modlin
发明人： Joseph Michael Haemer , Fu Chiung Chong , Douglas N. Modlin
IPC分类号： H05K7/06
CPC分类号： H05K7/1061 , G01R1/06711 , G01R1/06727 , G01R1/07314 , G01R3/00 , H05K3/4092 , Y10S439/912 , Y10T29/49004
摘要： Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a stiffening structure and a compliant carrier structure, such as a decal or screen, which is fixedly attached to the probe chip substrate.
摘要翻译：公开了增强的集成电路探针卡和封装组件的几个实施例，其延伸了MEMS和薄膜制造的探针的机械顺应性，使得这些类型的弹簧探针结构可用于测试半导体上的一个或多个集成电路晶圆。公开了在商业晶片探测设备中提供紧密的信号垫间距顺应性和/或实现高水平并行测试的探针卡组件的几个实施例。在一些优选实施例中，探针卡组件结构包括可分离的标准部件，这降低了组装制造成本和制造时间。这些结构和组件能够以晶圆形式进行高速测试。这些探头还内置了集成电路和MEMS或薄膜制造的弹簧尖端和基板上的探针布局结构的机械保护。替代卡组件结构包括固定结合到探针芯片基板上的加强结构和柔性载体结构，例如贴花或屏蔽。

2. 发明授权

US06917525B2 Construction structures and manufacturing processes for probe card assemblies and packages having wafer level springs 失效
标题翻译：具有晶片级弹簧的探针卡组件和封装的结构和制造工艺
公开(公告)号：US06917525B2
公开(公告)日：2005-07-12
申请号：US10178103
申请日：2002-06-24
申请人： Sammy Mok , Fu Chiung Chong , Frank John Swiatowiec , Syamal Kumar Lahiri , Joseph Michael Haemer
发明人： Sammy Mok , Fu Chiung Chong , Frank John Swiatowiec , Syamal Kumar Lahiri , Joseph Michael Haemer
IPC分类号： G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H05K3/40 , H05K7/10 , H05K7/06
CPC分类号： G01R1/07378 , G01R1/06716 , G01R1/06727 , G01R1/07342 , G01R3/00 , G01R31/2889 , H01L2224/16225 , H01L2924/15311 , H05K3/4092 , H05K7/1061 , Y10S439/912
摘要： Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.
摘要翻译：公开了增强的集成电路探针卡和封装组件的几个实施例，其延伸了MEMS和薄膜制造的探针的机械顺应性，使得这些类型的弹簧探针结构可用于测试半导体上的一个或多个集成电路晶圆。公开了在商业晶片探测设备中提供紧密的信号垫间距顺应性和/或实现高水平并行测试的探针卡组件的几个实施例。在一些优选实施例中，探针卡组件结构包括可分离的标准部件，这降低了组装制造成本和制造时间。这些结构和组件能够以晶圆形式进行高速测试。这些探头还内置了集成电路和MEMS或薄膜制造的弹簧尖端和基板上的探针布局结构的机械保护。替代卡组合结构包括柔性载体结构，例如粘贴到探针芯片基底上的贴花或屏幕。

3. 发明授权

US08575954B2 Structures and processes for fabrication of probe card assemblies with multi-layer interconnect 失效
标题翻译：具有多层互连的探针卡组件的制造结构和工艺
公开(公告)号：US08575954B2
公开(公告)日：2013-11-05
申请号：US12525051
申请日：2008-01-31
申请人： Fu Chiung Chong , William R. Bottoms , Erh-Kong Chieh , Nim Cho Lam
发明人： Fu Chiung Chong , William R. Bottoms , Erh-Kong Chieh , Nim Cho Lam
IPC分类号： G01R31/00
CPC分类号： G01R31/2889 , G01R3/00 , H01L2924/14
摘要： Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.
摘要翻译：基于包括在预定位置处的多个集成电路的半导体晶片的布局，每个集成电路包括一组电连接焊盘，建立探针芯片接触器，在探针的探针侧具有单位标准单元芯片对应于每个排列的集成电路。单元标准单元在探针芯片接触器的探针侧进行了阶梯式重复，以建立晶圆级标准单元布局。探针芯片接触器的相对接触侧可连接到中心结构，例如， Z块或PC板，通常包括具有固定的X，Y和Z位置的固定的通孔阵列。探针芯片接触器的接触侧的路由优选地被自动路由，例如在一个或多个计算机上实现，以提供通过通孔的基板与通过通孔的Z块之间的电连接。

4. 发明申请

US20090153165A1 High Density Interconnect System Having Rapid Fabrication Cycle 失效
标题翻译：高密度互连系统具有快速制造周期
公开(公告)号：US20090153165A1
公开(公告)日：2009-06-18
申请号：US12354520
申请日：2009-01-15
申请人： Fu Chiung Chong , Andrew Kao , Douglas McKay , Anna Litza , Douglas Modlin , Sammy Mok , Nitin Parekh , Frank John Swiatowiec , Zhaohui Shan
发明人： Fu Chiung Chong , Andrew Kao , Douglas McKay , Anna Litza , Douglas Modlin , Sammy Mok , Nitin Parekh , Frank John Swiatowiec , Zhaohui Shan
IPC分类号： G01R31/02
CPC分类号： G01R31/02 , G01R1/073 , G01R1/07378 , G01R31/2889 , Y10T29/49117 , Y10T29/49222
摘要： An improved interconnection system and method is described, such as for connectors, socket assemblies and/or probe card systems. An exemplary system comprises a probe card interface assembly (PCIA) for establishing electrical connections to a semiconductor wafer mounted in a prober. The PCIA comprises a motherboard parallel to the semiconductor wafer having an upper surface and an opposing lower planar mounting surface, a reference plane defined by a least three points located between the lower surface of the motherboard and the wafer, at least one component located below the motherboard mounting surface, and a mechanism for adjusting the planarity of the reference plane with respect to the wafer. A probe chip having a plurality of spring probes extending there from is mountable and demountable from the PCIA, without the need for further planarity adjustment. The interconnection structures and methods preferably provide improved fabrication cycles.
摘要翻译：描述了改进的互连系统和方法，例如用于连接器，插座组件和/或探针卡系统。示例性系统包括用于建立到安装在探测器中的半导体晶片的电连接的探针卡接口组件（PCIA）。 PCIA包括平行于具有上表面和相对的下平面安装表面的半导体晶片的母板，由位于母板的下表面和晶片之间的至少三个点限定的参考平面，至少一个位于主板安装表面和用于调整参考平面相对于晶片的平面度的机构。具有从其延伸的多个弹簧探针的探针芯片可从PCIA安装和拆卸，而不需要进一步的平面度调节。互连结构和方法优选地提供改进的制造周期。

5. 发明授权

US07138818B2 Massively parallel interface for electronic circuit 失效
公开(公告)号：US07138818B2
公开(公告)日：2006-11-21
申请号：US11327728
申请日：2006-01-05
申请人： Fu Chiung Chong , Sammy Mok
发明人： Fu Chiung Chong , Sammy Mok
IPC分类号： G01R31/02
CPC分类号： G01R31/2863 , G01R1/06722 , G01R1/07342 , G01R3/00 , G01R31/2874 , G01R31/2889
摘要： Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.

6. 发明授权

US5973504A Programmable high-density electronic device testing 失效
标题翻译：可编程高密度电子设备测试
公开(公告)号：US5973504A
公开(公告)日：1999-10-26
申请号：US925369
申请日：1997-09-08
申请人： Fu Chiung Chong
发明人： Fu Chiung Chong
IPC分类号： G01R31/26 , G01R1/073 , G01R31/28 , G01R31/319 , H01L21/66 , G01R31/02
CPC分类号： G01R1/0735 , G01R31/31905 , G01R31/31908 , H01L2924/0002
摘要： Generally, in one aspect, apparatus features a structure for routing test signals between pads of a device under test and a tester circuit. The structure features a probe support that includes a substrate having contact points, one for each of the pads to be tested, a number of conductors for connection to the tester circuit, the number of conductors being fewer than the number of contact points on the substrate, and switching circuitry mounted on the probe support for routing the test signals between the conductors and the contact points. In another aspect, a method routes test signals between pads of a device under test and terminals of a tester circuit, the method features providing a test head in the vicinity of the device under test, the test head having a contact for each pad to be tested on the device under test and a separate conductor connecting each contact to a switching circuit located on the test head, passing test signals between the pads of the device under test and the switching circuit via the conductors, and passing test signals between the switching circuit and the terminals of the tester via wires that number fewer than half of the number of conductors on the test head.
摘要翻译：通常，在一个方面，装置具有用于在测试设备的焊盘和测试器电路之间路由测试信号的结构。该结构的特征在于探针支架，其包括具有接触点的基底，每个要测试的垫中的一个，用于连接到测试器电路的多个导体，导体的数量少于衬底上的接触点的数量以及安装在探针支架上的开关电路，用于在导体和接触点之间布置测试信号。另一方面，一种方法将被测设备的焊盘和测试器电路的端子之间的测试信号进行路由，该方法特征在于被测设备附近提供测试头，测试头具有用于每个焊盘的触点在被测设备上进行测试，以及将每个触点连接到位于测试头上的开关电路的单独导体，将被测器件的焊盘之间的测试信号和通过导体的开关电路通过测试信号，并将测试信号通过开关电路并且测试仪的端子数量少于测试头上导体数量的一半。

7. 发明授权

US07621761B2 Systems for testing and packaging integrated circuits 失效
公开(公告)号：US07621761B2
公开(公告)日：2009-11-24
申请号：US11781172
申请日：2007-07-20
申请人： Sammy Mok , Fu Chiung Chong , Roman Milter
发明人： Sammy Mok , Fu Chiung Chong , Roman Milter
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： G01R31/2889 , C23C18/00 , C25D7/00 , G01R1/06727 , G01R1/06755 , G01R1/07342 , G01R3/00 , G01R31/2863 , G01R31/2874 , H01L2924/01027 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H04L43/50 , H05K3/4092
摘要： Several embodiments of stress metal springs are disclosed, which typically comprise a plurality of stress metal layers that are established on a substrate, which are then controllably patterned and partially released from the substrate. An effective rotation angle is typically created in the formed stress metal springs, defining a looped spring structure. The formed springs provide high pitch compliant electrical contacts for a wide variety of interconnection systems, including chip scale semiconductor packages, high density interposer connectors, and probe contactors. Several embodiments of massively parallel interface integrated circuit test assemblies are also disclosed, comprising one or more substrates having stress metal spring contacts, to establish connections between one or more separated integrated circuits on a compliant wafer carrier.

8. 发明授权

US07137830B2 Miniaturized contact spring 失效
公开(公告)号：US07137830B2
公开(公告)日：2006-11-21
申请号：US10390994
申请日：2003-03-17
申请人： Syamal Kumar Lahiri , Frank Swiatowiec , Fu Chiung Chong , Sammy Mok , Erh-Kong Chieh , Roman L. Milter , Joseph M. Haemer , Chang-Ming Lin , Yi-Hsing Chen , David Thanh Doan
发明人： Syamal Kumar Lahiri , Frank Swiatowiec , Fu Chiung Chong , Sammy Mok , Erh-Kong Chieh , Roman L. Milter , Joseph M. Haemer , Chang-Ming Lin , Yi-Hsing Chen , David Thanh Doan
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： G01R3/00 , B81B3/0072 , B81B2201/018 , G01R1/06761 , H01L21/4853 , H01L23/49811 , H01L24/72 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01R12/57 , H01R12/718 , H01R13/24 , H01R13/2442 , H05K3/4092 , H05K7/1061
摘要： This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

9. 发明授权

US07009412B2 Massively parallel interface for electronic circuit 失效
公开(公告)号：US07009412B2
公开(公告)日：2006-03-07
申请号：US10918511
申请日：2004-08-12
申请人： Fu Chiung Chong , Sammy Mok
发明人： Fu Chiung Chong , Sammy Mok
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2863 , G01R1/06722 , G01R1/07342 , G01R3/00 , G01R31/2874 , G01R31/2889
摘要： Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes. The parallel interface assemblies provide tight signal pad pitch and compliance, and preferably enable the parallel testing or burn-in of multiple ICs, using commercial wafer probing equipment. In some preferred embodiments, the parallel interface assembly structures include separable standard electrical connector components, which reduces assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form.

10. 发明授权

US06799976B1 Construction structures and manufacturing processes for integrated circuit wafer probe card assemblies 失效
标题翻译：集成电路晶圆探针卡组件的结构和制造工艺
公开(公告)号：US06799976B1
公开(公告)日：2004-10-05
申请号：US09980040
申请日：2001-11-27
申请人： Sammy Mok , Fu Chiung Chong
发明人： Sammy Mok , Fu Chiung Chong
IPC分类号： H01R1200
CPC分类号： G01R1/07371 , G01R1/07378 , G01R3/00 , G01R31/2886 , G01R31/2887 , H05K3/4092 , H05K7/1061
摘要： Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Interleaved spring probe tip designs are defined which allow multiple probe contacts on very small integrated circuit pads. The shapes of probe tips are preferably defined to control the depth of probe tip penetration between a probe spring and a pad or trace on an integrated circuit device. Improved protective coating techniques for spring probes are also disclosed, offering increased reliability and extended useful service lives for probe card assemblies.
摘要翻译：公开了集成电路探针卡组件的几个实施例，其延伸了MEMS和薄膜制造的探针的机械顺应性，使得这些类型的弹簧探针结构可用于测试半导体晶片上的一个或多个集成电路。公开了在商业晶片探测设备中提供紧密的信号垫间距顺应性和/或实现高水平并行测试的探针卡组件的几个实施例。在一些优选实施例中，探针卡组件结构包括可分离的标准部件，这降低了组装制造成本和制造时间。这些结构和组件能够以晶圆形式进行高速测试。这些探头还内置了集成电路和MEMS或薄膜制造的弹簧尖端和基板上的探针布局结构的机械保护。定义了交错的弹簧探针尖端设计，允许在非常小的集成电路板上进行多个探针接触。探针尖端的形状优选地限定为控制探针尖端在探针弹簧和集成电路器件上的焊盘或迹线之间的深度。还公开了用于弹簧探针的改进的保护涂层技术，为探针卡组件提供增加的可靠性和延长的有用的使用寿命。

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