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1. 发明申请

US20080052482A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING CLOCK LATENCY ACCORDING TO REORDERING OF BURST DATA 失效
标题翻译：半导体存储器件和控制根据脉冲数据的时钟延迟的方法
公开(公告)号：US20080052482A1
公开(公告)日：2008-02-28
申请号：US11775780
申请日：2007-07-10
申请人： Joo-Sun CHOI , Won-Chang JUNG , Hi-Choon LEE , Sung-Min YIM , Chul-Woo PARK , Won-Il BAE
发明人： Joo-Sun CHOI , Won-Chang JUNG , Hi-Choon LEE , Sung-Min YIM , Chul-Woo PARK , Won-Il BAE
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C7/1072
摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.
摘要翻译：在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。半导体存储器件可以包括控制单元和等待时间控制单元。控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。延迟控制单元可以响应于等待时间控制信号来控制等待时间值。半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

2. 发明申请

US20090103374A1 MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME 有权
标题翻译：具有相同模式的存储器模块和存储器系统
公开(公告)号：US20090103374A1
公开(公告)日：2009-04-23
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
发明人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

3. 发明申请

US20120300555A1 INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：集成电路存储器件
公开(公告)号：US20120300555A1
公开(公告)日：2012-11-29
申请号：US13478774
申请日：2012-05-23
申请人： Choong-Sun SHIN , Joo-Sun CHOI
发明人： Choong-Sun SHIN , Joo-Sun CHOI
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C5/04 , G11C5/025 , G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4093 , G11C11/4097
摘要： A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.
摘要翻译：半导体存储器件包括形成在一个芯片上的多个存储区域，每个存储器区域具有形成为2K位密度或容量的多个易失性存储器单元，其中K是大于或等于0的整数以及用于输入和输出易失性存储器单元的数据的多个输入/输出（I / O）端子，以及控制用于将数据写入存储区域的写入操作的至少一个外围区域和用于读取数据的读取操作基于从外部输入的命令和地址从存储器区域。因此，存储区域的总体或整个密度对应于非标准（或中间）密度，使得半导体存储器件可具有临时密度。

4. 发明申请

US20120280731A1 PHASE-LOCKED-LOOP CIRCUIT INCLUDING DIGITALLY-CONTROLLED OSCILLATOR 有权
标题翻译：包括数字控制振荡器的锁相环电路
公开(公告)号：US20120280731A1
公开(公告)日：2012-11-08
申请号：US13291548
申请日：2011-11-08
申请人： Woogeun RHEE , He RUI , Xueyi YU , Tae-Young OH , Joo-Sun CHOI , Zhihua WANG
发明人： Woogeun RHEE , He RUI , Xueyi YU , Tae-Young OH , Joo-Sun CHOI , Zhihua WANG
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/087 , H03L7/093 , H03L2207/06
摘要： A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.
摘要翻译：提供了锁相环（PLL）电路。 PLL电路包括相位/频率检测器，数字滤波器，数字低通滤波器（LPF），数字控制振荡器（DCO）和分频器。数字LPF以数字模式对最低有效位的第一数字数据进行低通滤波，并产生滤波后的第二数字数据。 DCO对第二数字数据和第一数字数据的最高有效位执行数模转换以产生第一信号，基于第一信号产生振荡控制信号，并产生响应振荡的输出时钟信号到振荡控制信号。

5. 发明申请

US20090037800A1 DATA PARALLELIZING RECEIVER 有权
标题翻译：数据并行接收器
公开(公告)号：US20090037800A1
公开(公告)日：2009-02-05
申请号：US12183552
申请日：2008-07-31
申请人： Hoe-Ju CHUNG , Joo-Sun CHOI , Ken S. LIM
发明人： Hoe-Ju CHUNG , Joo-Sun CHOI , Ken S. LIM
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/091 , H03M13/6575
摘要： Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.
摘要翻译：提供了一种数据并行接收器，包括用于从外部接收串行数据作为分组的输入信号接收器，对串行数据进行采样，以输入顺序对准采样数据，并将对准的数据转换为并行数据以输出并行数据，循环冗余检查（CRC）部分计算器，用于接收并行数据，根据输入顺序将并行数据分组成组，并对每个组执行部分CRC计算，以顺序输出多个部分CRC计算结果，以及CRC部分用于接收多个部分CRC计算结果的计算合并，并将部分CRC计算结果合并到输出CRC计算数据。

6. 发明申请

US20070086228A1 MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME 有权
标题翻译：具有相同模式的存储器模块和存储器系统
公开(公告)号：US20070086228A1
公开(公告)日：2007-04-19
申请号：US11379345
申请日：2006-04-19
申请人： Joo-Sun CHOI
发明人： Joo-Sun CHOI
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1051 , G11C7/22 , G11C2207/107
摘要： A memory module includes a port configured to receive write data and command/address signals and multiple memory devices. The multiple memory devices include a first set of the memory devices, each memory device of the first set coupled to the port, and a second set of the memory devices, each memory device of the second set configured to receive associated write data and associated command/address signals for the memory device through at least one of the other memory devices of the first set and the second set.
摘要翻译：存储器模块包括被配置为接收写入数据和命令/地址信号的端口以及多个存储器件。多个存储器设备包括第一组存储器件，耦合到端口的第一组的每个存储器件和第二组存储器件，第二组的每个存储器件被配置为接收相关联的写入数据和相关联的命令通过第一组和第二组的其他存储器件中的至少一个存储器件的/地址信号。

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