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1. 发明申请

US20090103374A1 MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME 有权
标题翻译：具有相同模式的存储器模块和存储器系统
公开(公告)号：US20090103374A1
公开(公告)日：2009-04-23
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
发明人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

2. 发明申请

US20130120043A1 DELAY-LOCKED-LOOP CIRCUIT 有权
标题翻译：延迟锁定电路
公开(公告)号：US20130120043A1
公开(公告)日：2013-05-16
申请号：US13729412
申请日：2012-12-28
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： H03L7/08
CPC分类号： G11C8/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03L7/07 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
摘要翻译：公开了一种具有当外部时钟信号具有低频率时操作的DLL的延迟锁定环路（DLL）电路，以及当外部时钟信号具有高频率时操作的DLL。 DLL电路包括第一DLL和第二DLL。当外部时钟信号具有低频率时，第一个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第一个内部时钟信号。当外部时钟信号具有高频率时，第二个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第二个内部时钟信号。

3. 发明申请

US20120254390A1 APPARATUS AND METHOD FOR TRANSMITTING PUSH NOTIFICATION MESSAGE 有权
标题翻译：用于发送推挽信息的装置和方法
公开(公告)号：US20120254390A1
公开(公告)日：2012-10-04
申请号：US13435884
申请日：2012-03-30
申请人： Jung-Hwan CHOI , Hee Seo , Ka-Ram Ko , In-Gyu Kim
发明人： Jung-Hwan CHOI , Hee Seo , Ka-Ram Ko , In-Gyu Kim
IPC分类号： G06F15/173
CPC分类号： H04L51/30 , H04L51/38
摘要： Provided is an apparatus and method for transmitting a push notification message. To this end, connection is performed with a mobile terminal, and if a push notification message is received from a push notification service providing server, the received push notification message is transmitted to the mobile terminal, and when disconnected from the mobile terminal, a push notification message received after the disconnection is stored, such that transmission of the push notification message can be guaranteed.
摘要翻译：提供了一种用于发送推送通知消息的装置和方法。为此，与移动终端进行连接，如果从推送通知服务提供服务器接收到推送通知消息，则将接收到的推送通知消息发送到移动终端，并且当与移动终端断开连接时，推送在断开连接之后接收的通知消息被存储，使得能够保证推送通知消息的发送。

4. 发明申请

US20110164462A1 DELAY-LOCKED-LOOP CIRCUIT, SEMICONDUCTOR DEVICE AND MEMORY SYSTEM HAVING THE DELAY-LOCKED-LOOP CIRCUIT 有权
标题翻译：延迟锁定环路，半导体器件和具有延迟环路的存储器系统
公开(公告)号：US20110164462A1
公开(公告)日：2011-07-07
申请号：US12979814
申请日：2010-12-28
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： G11C7/00 , H03L7/06
CPC分类号： G11C8/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03L7/07 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
摘要翻译：公开了一种具有当外部时钟信号具有低频率时操作的DLL的延迟锁定环路（DLL）电路，以及当外部时钟信号具有高频率时操作的DLL。 DLL电路包括第一DLL和第二DLL。当外部时钟信号具有低频率时，第一个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第一个内部时钟信号。当外部时钟信号具有高频率时，第二个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第二个内部时钟信号。

5. 发明申请

US20100194457A1 DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：延迟锁定环路电路和包括其的半导体存储器件
公开(公告)号：US20100194457A1
公开(公告)日：2010-08-05
申请号：US12686633
申请日：2010-01-13
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block.
摘要翻译：延迟锁定环电路包括：延迟锁定环路块，接收外部时钟并产生延迟锁定的内部时钟; 连接到所述延迟锁定环路块并校正所述内部时钟的占空比的占空比校正块; 以及误差检测单元，比较占空比校正块的第一和第二泵输出节点的电压，以检测占空比校正块的操作误差。

6. 发明申请

US20160117101A1 MEMORY SYSTEM, MEMORY MODULE, AND METHODS OF OPERATING THE SAME 有权
标题翻译：存储器系统，存储器模块及其操作方法
公开(公告)号：US20160117101A1
公开(公告)日：2016-04-28
申请号：US14803116
申请日：2015-07-20
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： G06F3/06 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0635 , G06F3/0659 , G06F3/0688 , G11C5/04 , G11C7/10
摘要： A memory system includes a memory controller, a first memory module and second through k-th memory modules. The first memory module is directly coupled to the memory controller without any other memory modules communicatively coupled therebetween, through a first memory bus, and the first memory module exchanges first data with the memory controller.The second through k-th memory modules are coupled to the first memory module with a multi-drop connection through a second memory bus and the second through k-th memory modules exchange second data with the memory controller via the first memory module.
摘要翻译：存储器系统包括存储器控制器，第一存储器模块和第二至第k存储器模块。第一存储器模块通过第一存储器总线直接耦合到存储器控制器，而没有通过其间通信耦合的任何其它存储器模块，并且第一存储器模块与存储器控制器交换第一数据。第二至第k个存储器模块通过第二存储器总线通过多点连接耦合到第一存储器模块，并且第二至第k存储器模块经由第一存储器模块与存储器控制器交换第二数据。

7. 发明申请

US20110153939A1 SEMICONDUCTOR DEVICE, CONTROLLER ASSOCIATED THEREWITH, SYSTEM INCLUDING THE SAME, AND METHODS OF OPERATION 有权
标题翻译：半导体器件，与其相关的控制器，包括其的系统和操作方法
公开(公告)号：US20110153939A1
公开(公告)日：2011-06-23
申请号：US12946334
申请日：2010-11-15
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G11C7/12 , G06F13/1663 , G06F13/1668 , G11C11/401 , G11C11/407 , G11C11/4096
摘要： In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions. The enabled processing function may be performed based on a signal received over a single pin associated with the group of processing functions. In another embodiment, the semiconductor device includes a data control unit configured to process data read from a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a read operation. Here, the group of processing functions including at least two processing functions.
摘要翻译：在一个实施例中，半导体器件包括被配置为选择性地处理用于写入存储器的数据的数据控制单元。数据控制单元被配置为在写入操作期间基于模式寄存器命令从一组处理功能中启用处理功能，该组处理功能包括至少三个处理功能。可以基于通过与该组处理功能相关联的单个引脚接收的信号来执行使能处理功能。在另一实施例中，半导体器件包括被配置为处理从存储器读取的数据的数据控制单元。数据控制单元被配置为在读取操作期间基于模式寄存器命令启用来自一组处理功能的处理功能。这里，一组处理功能包括至少两个处理功能。

8. 发明申请

US20090021286A1 PSEUDO DIFFERENTIAL OUTPUT BUFFER, MEMORY CHIP AND MEMORY SYSTEM 有权
标题翻译： PSEUDO差分输出缓冲器，存储器芯片和存储器系统
公开(公告)号：US20090021286A1
公开(公告)日：2009-01-22
申请号：US12243116
申请日：2008-10-01
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： H03K3/00
CPC分类号： H04L25/0278 , G11C7/1051 , G11C7/1057 , H03K19/018528 , H04L25/028
摘要： An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.
摘要翻译：输出缓冲器包括第一和第二输入晶体管，第一和第二输出负载以及电流源。第一和第二输入晶体管具有共同耦合的第一电流电极和分别耦合到第一差分输入信号和第二差分输入信号的控制电极。第一和第二输出负载分别耦合在第一电源电压和第一和第二输入晶体管之间，其中输出端耦合到第一输出负载耦合到第一输入晶体管的节点。电流源耦合在第一和第二输入晶体管的第一电流电极和第二电源电压之间，其中第二输出负载具有基本上是第一输出负载的阻抗值的一半的阻抗值。因此，可以通过单个输出端子输出差分输出信号。

9. 发明申请

US20180122741A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 审中-公开
公开(公告)号：US20180122741A1
公开(公告)日：2018-05-03
申请号：US15679662
申请日：2017-08-17
申请人： Young-Chul CHO , Min-Su AHN , Jung-Hwan CHOI
发明人： Young-Chul CHO , Min-Su AHN , Jung-Hwan CHOI
IPC分类号： H01L23/522 , H01L23/00 , H01L23/532
CPC分类号： H01L23/5226 , H01L23/5227 , H01L23/525 , H01L23/53295 , H01L24/05 , H01L24/08 , H01L24/48 , H01L27/0248 , H01L2224/02166 , H01L2224/02331 , H01L2224/05024 , H01L2224/05554 , H01L2224/06135 , H01L2224/48227 , H01L2224/48463 , H01L2224/49171 , H01L2924/00014 , H01L2224/45099
摘要： A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

10. 发明申请

US20140169119A1 MEMORY SYSTEM HAVING DELAY-LOCKED-LOOP CIRCUIT 有权
标题翻译：具有延迟锁定电路的存储器系统
公开(公告)号：US20140169119A1
公开(公告)日：2014-06-19
申请号：US14185412
申请日：2014-02-20
申请人： Jung-Hwan CHOI
发明人： Jung-Hwan CHOI
IPC分类号： G11C8/18
CPC分类号： G11C8/00 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03L7/07 , H03L7/08 , H03L7/0814 , H03L7/0816 , H03L7/0818
摘要： A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
摘要翻译：公开了一种具有当外部时钟信号具有低频率时操作的DLL的延迟锁定环路（DLL）电路，以及当外部时钟信号具有高频率时操作的DLL。 DLL电路包括第一DLL和第二DLL。当外部时钟信号具有低频率时，第一个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第一个内部时钟信号。当外部时钟信号具有高频率时，第二个DLL调整外部时钟信号的延迟时间，以产生与外部时钟信号同步的第二个内部时钟信号。

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