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1. 发明授权

US08741672B2 Crystallization method of thin film transistor, thin film transistor array panel and manufacturing method for thin film transistor array panel 有权
标题翻译：薄膜晶体管，薄膜晶体管阵列面板的结晶方法及薄膜晶体管阵列面板的制造方法
公开(公告)号：US08741672B2
公开(公告)日：2014-06-03
申请号：US13535007
申请日：2012-06-27
申请人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
发明人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78663 , H01L27/1222 , H01L27/1285
摘要： Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
摘要翻译：本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。

2. 发明申请

US20130037813A1 CRYSTALLIZATION METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：薄膜晶体管，薄膜晶体管阵列的结晶方法和薄膜晶体管阵列的制造方法
公开(公告)号：US20130037813A1
公开(公告)日：2013-02-14
申请号：US13535007
申请日：2012-06-27
申请人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
发明人： Joo-Han Kim , Hwa-Dong Jung , Wan-Soon Lim , Jee-Hun Lim , Joo Seok Yeom , Tae-Kyung Yim , Jae-Hak Lee , Hyuk Soon Kwon , Hyoung Cheol Lee , Jeong-Ju Park , Se-Myung Kwon , So-Young Koo
IPC分类号： H01L33/08
CPC分类号： H01L29/78663 , H01L27/1222 , H01L27/1285
摘要： Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
摘要翻译：本发明的示例性实施例公开了一种制造薄膜晶体管阵列面板的方法，其具有缩短的总体处理时间并提供均匀的结晶。本发明的示例性实施例还公开了一种薄膜晶体管的结晶方法，包括在基板上形成包括第一像素区域，第二像素区域和第三像素区域的半导体层。结晶方法包括使用微透镜阵列结晶对应于薄膜晶体管的沟道区的半导体层的一部分。

3. 发明授权

US10101660B2 Methods of forming patterns of semiconductor devices 有权
公开(公告)号：US10101660B2
公开(公告)日：2018-10-16
申请号：US15345910
申请日：2016-11-08
申请人： Jeong-Ju Park , Seung-Chul Kwon , Eun-Sung Kim , Kyeong-Mi Lee , Shi-Yong Yi , Tsuyosh Kurosawa , Katsumi Ohmori , Tasuku Matsumiya
发明人： Jeong-Ju Park , Seung-Chul Kwon , Eun-Sung Kim , Kyeong-Mi Lee , Shi-Yong Yi , Tsuyosh Kurosawa , Katsumi Ohmori , Tasuku Matsumiya
IPC分类号： G03F7/004 , G03F7/16 , H01L27/108 , C08F20/28 , B82Y10/00 , B82Y40/00 , C08L53/00 , G03F7/20 , G03F7/00 , G03F7/40 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L49/02
摘要： In a method of forming patterns, an object layer is formed on a substrate. Guide patterns are formed on the object layer. A brush layer is formed using a brush polymer on surfaces of the guide patterns. The brush polymer includes at least one of a first brush polymer and a second brush polymer. The first brush polymer includes a hydrophobic repeating unit and a hydrophilic terminal group having at least two hydroxyl groups. The second brush polymer includes a hydrophobic repeating unit and a hydrophilic random repeating unit having a hydroxyl group. A self-aligned layer is formed using a block copolymer on the brush layer to form blocks aligned around the guide patterns. At least a portion of the blocks is transferred to the object layer.

4. 发明申请

US20110300712A1 Methods of Forming a Photoresist Pattern Using Plasma Treatment of Photoresist Patterns 审中-公开
标题翻译：使用等离子体处理光刻胶图案形成光刻胶图案的方法
公开(公告)号：US20110300712A1
公开(公告)日：2011-12-08
申请号：US13103375
申请日：2011-05-09
申请人： Kyoung-Mi Kim , Jeong-Ju Park , Mi-Ra Park , Bo-Hee Lee , Jae-Ho Kim , Young-Ho Kim
发明人： Kyoung-Mi Kim , Jeong-Ju Park , Mi-Ra Park , Bo-Hee Lee , Jae-Ho Kim , Young-Ho Kim
IPC分类号： H01L21/308 , H01L21/312
CPC分类号： H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , H01L27/11521
摘要： Methods of forming a photoresist pattern include forming a first photoresist pattern on a substrate and treating the first photoresist pattern with plasma that modifies etching characteristics of the first photoresist pattern. This modification may include making the first photoresist pattern more susceptible to removal during subsequent processing. The plasma-treated first photoresist pattern is covered with a second photoresist layer, which is patterned into a second photoresist pattern that contacts sidewalls of the plasma-treated first photoresist pattern. The plasma-treated first photoresist pattern is selectively removed from the substrate to reveal the remaining second photoresist pattern. The second photoresist pattern is used as an etching mask during the selective etching of a portion of the substrate (e.g., target layer). The use of the second photoresist pattern as an etching mask may yield narrower linewidths in the etched portion of the substrate than are achievable using the first photoresist pattern alone.
摘要翻译：形成光致抗蚀剂图案的方法包括在基板上形成第一光致抗蚀剂图案，并用等离子体处理第一光致抗蚀剂图案，其改变第一光致抗蚀剂图案的蚀刻特性。该修改可以包括使第一光致抗蚀剂图案在随后的处理期间更易于去除。等离子体处理的第一光致抗蚀剂图案被第二光致抗蚀剂层覆盖，第二光致抗蚀剂层被图案化成与等离子体处理的第一光致抗蚀剂图案的侧壁接触的第二光致抗蚀剂从衬底选择性地去除等离子体处理的第一光致抗蚀剂图案以显示剩余的第二光致抗蚀剂图案。在选择性蚀刻基板（例如，目标层）的一部分期间，将第二光致抗蚀剂图案用作蚀刻掩模。使用第二光致抗蚀剂图案作为蚀刻掩模可以在衬底的蚀刻部分中产生比仅使用第一光致抗蚀剂图案可实现的更窄的线宽。

5. 发明申请

US20050095782A1 Lower electrode contact structure and method of forming the same 失效
标题翻译：下电极接触结构及其形成方法
公开(公告)号：US20050095782A1
公开(公告)日：2005-05-05
申请号：US11000943
申请日：2004-12-02
申请人： Jeong-Ju Park
发明人： Jeong-Ju Park
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/76831 , H01L21/76834 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Lower electrode contact structures and methods of forming the same provide an interface having a large surface area between a lower electrode and the underlying layers. The lower electrode is in contact with a contact plug and an insulation layer in which the contact plug is buried. At least one supporting layer protrudes upright along the outer peripheral edge of the top surface of the contact plug. The interface between the lower electrode and the underlying layers is thus increased by the supporting layer(s) so that the lower electrode and the underlying layers will solidly adhere to each other.
摘要翻译：下电极接触结构及其形成方法提供了在下电极和下层之间具有大表面积的界面。下电极与接触插塞和绝缘层接触，其中接触插头被埋入其中。至少一个支撑层沿着接触插塞的上表面的外周缘直立突出。因此，下电极和下层之间的界面由支撑层增加，使得下电极和下层将彼此牢固地粘附。

6. 发明授权

US08551689B2 Methods of manufacturing semiconductor devices using photolithography 有权
标题翻译：使用光刻制造半导体器件的方法
公开(公告)号：US08551689B2
公开(公告)日：2013-10-08
申请号：US13117667
申请日：2011-05-27
申请人： Mi-Ra Park , Kyoung-Mi Kim , Jeong-Ju Park , Bo-Hee Lee , Jae-Ho Kim , Young-Ho Kim
发明人： Mi-Ra Park , Kyoung-Mi Kim , Jeong-Ju Park , Bo-Hee Lee , Jae-Ho Kim , Young-Ho Kim
IPC分类号： G03F7/26
CPC分类号： H01L21/0273 , G03F7/0035 , G03F7/091 , G03F7/40
摘要： A method of manufacturing a semiconductor device using a photolithography process may include forming an anti-reflective layer and a first photoresist film on a lower surface. The first photoresist film may be exposed to light and a first photoresist pattern having a first opening may be formed by developing the first photoresist film. A plasma treatment can be performed on the first photoresist pattern and a second photoresist film may be formed on the first photoresist pattern, which may be exposed to light. A second photoresist pattern may be formed to have a second opening by developing the second photoresist film. Here, the second opening may be substantially narrower than the first opening.
摘要翻译：使用光刻工艺制造半导体器件的方法可以包括在下表面上形成抗反射层和第一光致抗蚀剂膜。可以将第一光致抗蚀剂膜暴露于光，并且可以通过显影第一光致抗蚀剂膜来形成具有第一开口的第一光致抗蚀剂图案。可以在第一光致抗蚀剂图案上进行等离子体处理，并且可以在可以暴露于光的第一光致抗蚀剂图案上形成第二光致抗蚀剂膜。可以通过显影第二光致抗蚀剂膜来形成第二光致抗蚀剂图案以具有第二开口。这里，第二开口可以比第一开口窄得多。

7. 发明申请

US20070224758A1 Semiconductor memory device and related fabrication method 审中-公开
标题翻译：半导体存储器件及相关制造方法
公开(公告)号：US20070224758A1
公开(公告)日：2007-09-27
申请号：US11516750
申请日：2006-09-07
申请人： Jeong-Ju Park
发明人： Jeong-Ju Park
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L21/76831 , H01L21/76834 , H01L27/10855
摘要： Embodiments of the invention provide a semiconductor memory device and a method for fabricating the semiconductor memory device. The semiconductor memory device comprises a source region and a drain region disposed in a semiconductor substrate; a buried contact disposed on and electrically connected to the source region of the transistor; and a direct contact disposed on and electrically connected to the drain region of the transistor, wherein an upper surface of the direct contact is disposed at a different height than an upper surface of the buried contact. The semiconductor memory device further comprises a bit line disposed on and electrically connected to the direct contact and thereby electrically connected to the drain region; and a lower electrode of a capacitor disposed on and electrically connected to the buried contact and thereby electrically connected to the source region.
摘要翻译：本发明的实施例提供半导体存储器件和制造半导体存储器件的方法。半导体存储器件包括设置在半导体衬底中的源极区域和漏极区域; 设置在晶体管的源极区域上并与之电连接的埋入触点; 以及设置在晶体管的漏极区域并电连接到晶体管的漏极区域的直接接触，其中直接接触件的上表面设置在与埋入接触件的上表面不同的高度处。所述半导体存储器件还包括位线，其布置在所述直接触点上并电连接到所述直接触点，从而电连接到所述漏极区; 以及电容器的下电极，其布置在所述埋入触点上并电连接到所述掩埋触点，从而电连接到所述源极区。

8. 发明申请

US20050273680A1 Semiconductor device having buffer layer pattern and method of forming same 审中-公开
标题翻译：具有缓冲层图案的半导体器件及其形成方法
公开(公告)号：US20050273680A1
公开(公告)日：2005-12-08
申请号：US11122059
申请日：2005-05-05
申请人： Jeong-Ju Park
发明人： Jeong-Ju Park
IPC分类号： H01L21/28 , G11C29/00 , H01L21/768 , H01L21/8242 , H01L23/522
CPC分类号： H01L21/76895 , H01L21/76834 , H01L23/5226 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a buffer layer pattern and a related method of manufacture are disclosed. The semiconductor device comprises at least two bit line patterns formed on a semiconductor substrate having a buried insulating interlayer. Each bit line pattern is formed of a bit line and a bit line capping layer pattern formed on the bit line. A buffer layer pattern is formed to cover one of the bit line patterns, and bit line spacers are formed on sidewalls of the remaining bit line patterns. A planarized insulating interlayer covers the buffer layer pattern and the bit line spacers. A bit line contact hole passing through the planarized insulating interlayer, the buffer layer pattern, and the bit line capping layer pattern, is formed on the bit line.
摘要翻译：公开了一种具有缓冲层图案和相关制造方法的半导体器件。半导体器件包括形成在具有掩埋绝缘中间层的半导体衬底上的至少两个位线图案。每个位线图案由位线和形成在位线上的位线覆盖层图案形成。形成缓冲层图形以覆盖位线图案之一，并且位线间隔件形成在剩余位线图案的侧壁上。平坦化的绝缘夹层覆盖缓冲层图案和位线间隔物。在位线上形成穿过平坦化绝缘夹层，缓冲层图案和位线封盖层图案的位线接触孔。

9. 发明授权

US06861690B2 Lower electrode contact structure and method of forming the same 失效
公开(公告)号：US06861690B2
公开(公告)日：2005-03-01
申请号：US10634898
申请日：2003-08-06
申请人： Jeong-Ju Park
发明人： Jeong-Ju Park
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L25/208 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/91 , H01L21/76831 , H01L21/76834 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Lower electrode contact structures and methods of forming the same provide an interface having a large surface area between a lower electrode and the underlying layers. The lower electrode is in contact with a contact plug and an insulation layer in which the contact plug is buried. At least one supporting layer protrudes upright along the outer peripheral edge of the top surface of the contact plug. The interface between the lower electrode and the underlying layers is thus increased by the supporting layer(s) so that the lower electrode and the underlying layers will solidly adhere to each other.

10. 发明申请

US20110294072A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING PHOTOLITHOGRAPHY 有权
标题翻译：使用光刻技术制造半导体器件的方法
公开(公告)号：US20110294072A1
公开(公告)日：2011-12-01
申请号：US13117667
申请日：2011-05-27
申请人： Mi-Ra PARK , Kyoung-Mi Kim , Jeong-Ju Park , Bo-Hee Lee , Jae-Ho Kim , Young-Ho Kim
发明人： Mi-Ra PARK , Kyoung-Mi Kim , Jeong-Ju Park , Bo-Hee Lee , Jae-Ho Kim , Young-Ho Kim
IPC分类号： G03F7/20
CPC分类号： H01L21/0273 , G03F7/0035 , G03F7/091 , G03F7/40
摘要： A method of manufacturing a semiconductor device using a photolithography process may include forming an anti-reflective layer and a first photoresist film on a lower surface. The first photoresist film may be exposed to light and a first photoresist pattern having a first opening may be formed by developing the first photoresist film. A plasma treatment can be performed on the first photoresist pattern and a second photoresist film may be formed on the first photoresist pattern, which may be exposed to light. A second photoresist pattern may be formed to have a second opening by developing the second photoresist film. Here, the second opening may be substantially narrower than the first opening.
摘要翻译：使用光刻工艺制造半导体器件的方法可以包括在下表面上形成抗反射层和第一光致抗蚀剂膜。可以将第一光致抗蚀剂膜暴露于光，并且可以通过显影第一光致抗蚀剂膜来形成具有第一开口的第一光致抗蚀剂图案。可以在第一光致抗蚀剂图案上进行等离子体处理，并且可以在可以暴露于光的第一光致抗蚀剂图案上形成第二光致抗蚀剂膜。可以通过显影第二光致抗蚀剂膜来形成第二光致抗蚀剂图案以具有第二开口。这里，第二开口可以比第一开口窄得多。

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