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1. 发明申请

US20100237466A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20100237466A1
公开(公告)日：2010-09-23
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L29/92
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

2. 发明授权

US08704283B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08704283B2
公开(公告)日：2014-04-22
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

3. 发明申请

US20120225530A1 METHODS OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20120225530A1
公开(公告)日：2012-09-06
申请号：US13400993
申请日：2012-02-21
申请人： Jong-Kyu KIM , Sangsup Jeong , Kukhan Yoon , Junsoo Lee , SungII Cho , Yong-Joon Choi
发明人： Jong-Kyu KIM , Sangsup Jeong , Kukhan Yoon , Junsoo Lee , SungII Cho , Yong-Joon Choi
IPC分类号： H01L21/02 , H01L21/768
CPC分类号： H01L28/91 , H01L21/31144 , H01L27/0203 , H01L27/10817 , H01L27/10852
摘要： A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.
摘要翻译：一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起模式。在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。形成由支撑图案支撑的下电极。

4. 发明授权

US08927384B2 Methods of fabricating a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08927384B2
公开(公告)日：2015-01-06
申请号：US13400993
申请日：2012-02-21
申请人： Jong-Kyu Kim , Sangsup Jeong , Kukhan Yoon , Junsoo Lee , SungII Cho , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sangsup Jeong , Kukhan Yoon , Junsoo Lee , SungII Cho , Yong-Joon Choi
IPC分类号： H01L21/20 , H01L27/108 , H01L49/02 , H01L27/02 , H01L21/311
CPC分类号： H01L28/91 , H01L21/31144 , H01L27/0203 , H01L27/10817 , H01L27/10852
摘要： A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.
摘要翻译：一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起模式。在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。形成由支撑图案支撑的下电极。

5. 发明授权

US10622256B2 Method of manufacturing semiconductor device using multiple patterning techniques 有权
公开(公告)号：US10622256B2
公开(公告)日：2020-04-14
申请号：US15083248
申请日：2016-03-28
申请人： Seung-Jin Mun , Dong-Hoon Khang , Woo-Ram Kim , Cheol Kim , Dong-Seok Lee , Yong-Joon Choi , Seung-Mo Ha , Do-Hyoung Kim
发明人： Seung-Jin Mun , Dong-Hoon Khang , Woo-Ram Kim , Cheol Kim , Dong-Seok Lee , Yong-Joon Choi , Seung-Mo Ha , Do-Hyoung Kim
IPC分类号： H01L21/308 , H01L21/8234 , H01L23/544
CPC分类号： H01L21/823431 , H01L21/3086 , H01L23/544 , H01L2223/54426 , H01L2223/54453
摘要： A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.

6. 发明授权

US09190407B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09190407B2
公开(公告)日：2015-11-17
申请号：US14569597
申请日：2014-12-12
申请人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
发明人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
IPC分类号： H01L27/088 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L29/49
CPC分类号： H01L29/7853 , H01L21/30604 , H01L21/3065 , H01L21/3085 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0673 , H01L29/42364 , H01L29/4238 , H01L29/49 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
摘要翻译：半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。可以在第二绝缘体的顶表面上形成伪栅电极。还公开了其制造方法和修改方案。

7. 发明申请

US20170271351A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170271351A1
公开(公告)日：2017-09-21
申请号：US15612229
申请日：2017-06-02
申请人： Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
发明人： Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
IPC分类号： H01L27/11565 , H01L23/528 , H01L27/11573 , H01L27/11575 , H01L21/768 , H01L23/544 , H01L27/11582 , H01L23/522
CPC分类号： H01L27/11565 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/544 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2223/5442 , H01L2223/54433 , H01L2223/54453
摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

8. 发明授权

US08488386B2 Nonvolatile memory device for reducing interference between word lines and operation method thereof 失效
标题翻译：用于减少字线之间的干扰的非易失性存储器件及其操作方法
公开(公告)号：US08488386B2
公开(公告)日：2013-07-16
申请号：US13044683
申请日：2011-03-10
申请人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
发明人： Sung-Hoon Kim , Jai-Hyuk Song , Yong-Joon Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/28
摘要： Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line. Accordingly, when a program operation is performed, a charge loss of a memory cell connected to a word line adjacent to a dummy word line can be reduced by changing a voltage applied to the dummy word line according to a select word line.
摘要翻译：提供一种非易失性存储器件及其操作方法。根据本发明构思的实施例的非易失性存储器件可以包括串选择线; 地选线; 与地面选择线相邻的虚拟字线; 与虚拟字线相邻的第一字线; 以及设置在所述串选择线和所述第一字线之间的第二字线。非易失性存储器件被配置为向虚拟字线施加电压。当编程连接到第一字线的存储单元时，低于施加到第二字线的电压的第一虚拟字线电压被施加到虚拟字线。当编程连接到第二字线的存储单元时，施加到第一字线的电压和第一虚拟字线电压之间的第二虚拟字线电压被施加到伪字线。因此，当执行编程操作时，可以通过根据选择字线改变施加到虚拟字线的电压来减少连接到与虚拟字线相邻的字线的存储单元的电荷损失。

9. 发明授权

US06828637B2 Semiconductor memory devices having dummy active regions 有权
标题翻译：半导体存储器件具有虚拟有源区
公开(公告)号：US06828637B2
公开(公告)日：2004-12-07
申请号：US10794533
申请日：2004-03-05
申请人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
发明人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
IPC分类号： H01L2976
CPC分类号： H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.
摘要翻译：提供了具有虚设有源区的半导体存储器件，其包括多个平行的主有效区和与主有效区的端部耦合的虚拟有源区。主要优选的有源区域被布置在主存储单元阵列区域中并且延伸到或通过围绕主存储单元阵列区域的虚设单元阵列区域。此外，虚拟有源区域垂直于主要有源区域。冗余单元阵列区域可以介于主存储单元阵列区域和虚设单元阵列区域之间。在这种情况下，主要有源区域通过冗余单元阵列区域扩展到虚拟单元阵列区域。

10. 发明授权

US10090314B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US10090314B2
公开(公告)日：2018-10-02
申请号：US15612229
申请日：2017-06-02
申请人： Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
发明人： Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
IPC分类号： H01L27/115 , H01L27/11565 , H01L27/11582 , H01L21/768 , H01L23/544 , H01L27/11573 , H01L27/11575 , H01L23/522 , H01L23/528 , H01L27/1157
摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

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