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1. 发明授权

US08843693B2 Non-volatile memory and method with improved data scrambling 有权
标题翻译：非易失性存储器和具有改进的数据加扰的方法
公开(公告)号：US08843693B2
公开(公告)日：2014-09-23
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/00 , G11C7/10 , G11C16/34 , G06F12/14
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的编程干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

2. 发明申请

US20120297111A1 Non-Volatile Memory And Method With Improved Data Scrambling 有权
标题翻译：非易失性存储器和改进的数据加扰方法
公开(公告)号：US20120297111A1
公开(公告)日：2012-11-22
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/02
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的程序干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

3. 发明授权

US08737125B2 Aggregating data latches for program level determination 有权
标题翻译：汇总数据锁存器进行程序级确定
公开(公告)号：US08737125B2
公开(公告)日：2014-05-27
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译：在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

4. 发明授权

US08473809B2 Data coding for improved ECC efficiency 有权
标题翻译：数据编码，提高ECC效率
公开(公告)号：US08473809B2
公开(公告)日：2013-06-25
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

5. 发明申请

US20140043897A1 AGGREGATING DATA LATCHES FOR PROGRAM LEVEL DETERMINATION 有权
标题翻译：用于计划级别确定的数据挂接
公开(公告)号：US20140043897A1
公开(公告)日：2014-02-13
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译：在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

6. 发明申请

US20110126080A1 DATA CODING FOR IMPROVED ECC EFFICIENCY 有权
标题翻译：数据编码提高ECC效率
公开(公告)号：US20110126080A1
公开(公告)日：2011-05-26
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

7. 发明授权

US08453726B2 Corrugated settling cup and a multi-cup uniform flux gas anchor 有权
标题翻译：波纹沉降杯和多杯均匀通量气锚
公开(公告)号：US08453726B2
公开(公告)日：2013-06-04
申请号：US12673064
申请日：2008-08-22
申请人： Demin Wang , Yan Wang , Jun Wan , Shumin Zhang , Rongjie Zhu , Li Li
发明人： Demin Wang , Yan Wang , Jun Wan , Shumin Zhang , Rongjie Zhu , Li Li
IPC分类号： E21B43/38
CPC分类号： E21B43/38 , E21B43/127 , F04B47/02
摘要： A corrugated settling cup (5) is provided, wherein the cup has a cup body, an opening and a location step (52) are provided at the bottom (55) of the cup body, several location holes (53) are formed at the top of the location step (52), location projections (54) corresponding to the location holes (53) are formed at the bottom (55) of the corrugated settling cup (5), wherein the external profile of the corrugated settling cup body rises along the axial direction in a corrugated shape. A multi-cup uniform flux gas anchor is provided, wherein the gas anchor includes a central pipe (7), several corrugated settling cups (5), several settling cups protection bodies (6) and a well-flushing valve (9), wherein the external profile of the corrugated settling cup body rises along the axial direction in a corrugated shape.
摘要翻译：提供了一种波纹沉降杯（5），其中杯体具有杯体，在杯体的底部（55）设有开口和位置台阶（52），多个位置孔（53）形成在在波纹沉降杯（5）的底部（55）形成位置台阶（52）的顶部，对应于定位孔（53）的定位突起（54），其中波纹沉降杯体的外部轮廓上升沿轴向以波纹形状。提供了一种多杯均匀的通量气体锚定器，其中气锚包括中心管（7），多个波纹沉降杯（5），多个沉降杯保护体（6）和井冲洗阀（9），其中波纹沉降杯体的外部轮廓沿轴向方向以波纹形状上升。

8. 发明授权

US08379454B2 Detection of broken word-lines in memory arrays 有权
标题翻译：检测存储器阵列中断字符
公开(公告)号：US08379454B2
公开(公告)日：2013-02-19
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。比较不同字线的程序循环计数的字间对比比较，以确定字线是否有缺陷。将沿着字线WLn的单元所需的编程脉冲的数量与前一字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值一个阈值值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

9. 发明授权

US08368137B2 Dual bit line metal layers for non-volatile memory 有权
标题翻译：用于非易失性存储器的双位线金属层
公开(公告)号：US08368137B2
公开(公告)日：2013-02-05
申请号：US11768468
申请日：2007-06-26
申请人： Nima Mokhlesi , Jun Wan
发明人： Nima Mokhlesi , Jun Wan
IPC分类号： H01L29/788
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/18 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.
摘要翻译：公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。位线在两个分离的金属层中的每一个中以4fpitch形成，并且布置成在每个层之间交替。在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

10. 发明申请

US20120281479A1 Detection of Broken Word-Lines in Memory Arrays 有权
标题翻译：在内存数组中检测破碎的字线
公开(公告)号：US20120281479A1
公开(公告)日：2012-11-08
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/10
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。一个例子考虑比较不同字线的程序循环计数以便确定字线是否有缺陷的字间对比比较。例如，将沿着字线WLn的单元所需的编程脉冲的数量与先前的字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值通过阈值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

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