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1. 发明授权

US09195587B2 Enhanced dynamic read process with single-level cell segmentation 有权
标题翻译：增强的动态读取过程与单级细胞分割
公开(公告)号：US09195587B2
公开(公告)日：2015-11-24
申请号：US13789536
申请日：2013-03-07
申请人： Mrinal Kochar , Piyush Sagdeo , Anubhav Khandelwal
发明人： Mrinal Kochar , Piyush Sagdeo , Anubhav Khandelwal
IPC分类号： G06F12/00 , G06F12/02 , G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G06F12/0246 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/349
摘要： A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside.
摘要翻译：针对计算机存储器内的多个单级单元逻辑组中的每一个的多个字线区域中的每一个确定动态读取盒指定。多个字线区域中的任何给定的一个字线区域的动态读取案例指定了用于读取多个字线区域中给定的一个字线区域内的每个字线的存储器单元的字线读取电压。单级单元逻辑组的数量被折叠成多级单元块。折叠包括使用对应于动态读取案例指定的字线读取电压来读取单个级别单元逻辑组中的每一个的多个字线区域中的每一个的每个字线的每个字线的存储器单元，读存储单元驻留。

2. 发明申请

US20140258590A1 Enhanced Dynamic Read Process with Single-Level Cell Segmentation 有权
标题翻译：增强动态读取过程与单级细胞分割
公开(公告)号：US20140258590A1
公开(公告)日：2014-09-11
申请号：US13789536
申请日：2013-03-07
申请人： Mrinal Kochar , Piyush Sagdeo , Anubhav Khandelwal
发明人： Mrinal Kochar , Piyush Sagdeo , Anubhav Khandelwal
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/349
摘要： A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside.
摘要翻译：针对计算机存储器内的多个单级单元逻辑组中的每一个的多个字线区域中的每一个确定动态读取盒指定。多个字线区域中的任何给定的一个字线区域的动态读取案例指定了用于读取多个字线区域中给定的一个字线区域内的每个字线的存储器单元的字线读取电压。单级单元逻辑组的数量被折叠成多级单元块。折叠包括使用对应于动态读取案例指定的字线读取电压来读取单个级别单元逻辑组中的每一个的多个字线区域中的每一个的每个字线的每个字线的存储器单元，读存储单元驻留。

3. 发明申请

US20130336059A1 BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT 有权
标题翻译：阻塞等级可靠性和成本提升
公开(公告)号：US20130336059A1
公开(公告)日：2013-12-19
申请号：US13527199
申请日：2012-06-19
申请人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
发明人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/349 , G11C29/56008 , G11C29/82 , G11C2029/4402
摘要： A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
摘要翻译：可以使用用于分级块的系统来改善存储器使用。诸如闪存卡之类的存储器块可以在可以标识每个块的“良好”级别或“坏”级别的滑动标度上分级，而不是二进制好或坏标识。该分级系统可以利用至少三个等级的等级，其可以通过基于每个块的各个等级更好地利用每个块来提高效率。块调平分级系统可用于优化最小化产量损失的竞争需求，同时最小化测试缺陷逃逸。

4. 发明授权

US08379454B2 Detection of broken word-lines in memory arrays 有权
标题翻译：检测存储器阵列中断字符
公开(公告)号：US08379454B2
公开(公告)日：2013-02-19
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。比较不同字线的程序循环计数的字间对比比较，以确定字线是否有缺陷。将沿着字线WLn的单元所需的编程脉冲的数量与前一字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值一个阈值值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

5. 发明申请

US20120281479A1 Detection of Broken Word-Lines in Memory Arrays 有权
标题翻译：在内存数组中检测破碎的字线
公开(公告)号：US20120281479A1
公开(公告)日：2012-11-08
申请号：US13101765
申请日：2011-05-05
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan
IPC分类号： G11C16/10
CPC分类号： G11C29/52 , G11C16/3418 , G11C16/3459 , G11C29/025
摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. One example considers an “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. For example, the number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的断字。一个例子考虑比较不同字线的程序循环计数以便确定字线是否有缺陷的字间对比比较。例如，将沿着字线WLn的单元所需的编程脉冲的数量与先前的字线（例如WLn或WL（n-1））所需的数字进行比较，以查看其是否超过该较早的值通过阈值。如果字线需要过多的脉冲数，相对于较早的字线，要完成编程，则将其视为有缺陷的。

6. 发明授权

US08953398B2 Block level grading for reliability and yield improvement 有权
标题翻译：块级分级可靠性和产量提高
公开(公告)号：US08953398B2
公开(公告)日：2015-02-10
申请号：US13527199
申请日：2012-06-19
申请人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
发明人： Dana Lee , Jianmin Huang , Mrinal Kochar , Ashish Ghai
IPC分类号： G11C7/00
CPC分类号： G11C16/349 , G11C29/56008 , G11C29/82 , G11C2029/4402
摘要： A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
摘要翻译：可以使用用于分级块的系统来改善存储器使用。诸如闪存卡之类的存储器块可以在可以标识每个块的“良好”级别或“坏”级别的滑动标度上分级，而不是二进制好或坏标识。该分级系统可以利用至少三个等级的等级，其可以通过基于每个块的各个等级更好地利用每个块来提高效率。块调平分级系统可用于优化最小化产量损失的竞争需求，同时最小化测试缺陷逃逸。

7. 发明授权

US08693259B2 Wordline-to-wordline stress configuration 有权
标题翻译：字线到字线应力配置
公开(公告)号：US08693259B2
公开(公告)日：2014-04-08
申请号：US13340437
申请日：2011-12-29
申请人： Mrinal Kochar , Jianmin Huang , Jun Wan , Jian Chen
发明人： Mrinal Kochar , Jianmin Huang , Jun Wan , Jian Chen
IPC分类号： G11C16/06
CPC分类号： G11C29/06 , G11C16/00 , G11C2029/1202
摘要： A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention.
摘要翻译：公开了一种用于在存储设备上执行字线到字线应力程序的方法和系统。可以执行应力程序以减少存储设备中的多级存储器单元中的状态变宽。但是，如果压力程序太频繁地执行，则可能会导致数据保留问题。为了在适当的时候执行压力程序，使用应力控制变量。应力控制变量可以指示存储设备的年龄（例如在存储设备中的存储器块上执行的擦除周期的数量）。压力控制变量被输入到查找表（或其他逻辑结构），查找表的输出指示是否执行字线到字线应力程序。以这种方式，可以执行应力程序以减少状态扩大，同时减少数据保留的不良影响。

8. 发明授权

US09235470B2 Adaptive EPWR (enhanced post write read) scheduling 有权
标题翻译：自适应EPWR（增强后写入读）调度
公开(公告)号：US09235470B2
公开(公告)日：2016-01-12
申请号：US14045294
申请日：2013-10-03
申请人： Abhijeet Bhalerao , Mrinal Kochar , Piyush Sagdeo
发明人： Abhijeet Bhalerao , Mrinal Kochar , Piyush Sagdeo
IPC分类号： G06F11/00 , G11C29/00 , G06F11/10 , G06F12/02 , G06F11/07
CPC分类号： G06F11/1068 , G06F11/0796 , G06F12/0246
摘要： A system and method for adaptive enhanced post write reads (EPWRs) is provided. An error rate of a block of solid state memory may be determined. Foldings may be performed more times between two consecutive enhanced post write reads on the block when the determined error rate of the block is a lower value than when the determined error rate is a higher value. The foldings may be performed by folding data into the block of the solid state memory.
摘要翻译：提供了一种用于自适应增强后写入读取（EPWR）的系统和方法。可以确定固态存储器块的错误率。当块的确定的错误率比确定的错误率是较高值时的值低的情况下，可以在块上的两个连续增强的后写入读取之间执行折叠。折叠可以通过将数据折叠到固态存储器的块中来执行。

9. 发明申请

US20150100851A1 ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING 有权
标题翻译：自适应EPWR（增强后读写）调度
公开(公告)号：US20150100851A1
公开(公告)日：2015-04-09
申请号：US14045294
申请日：2013-10-03
申请人： Abhijeet Bhalerao , Mrinal Kochar , Piyush Sagdeo
发明人： Abhijeet Bhalerao , Mrinal Kochar , Piyush Sagdeo
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F11/0796 , G06F12/0246
摘要： A system and method for adaptive enhanced post write reads (EPWRs) is provided. An error rate of a block of solid state memory may be determined. Foldings may be performed more times between two consecutive enhanced post write reads on the block when the determined error rate of the block is a lower value than when the determined error rate is a higher value. The foldings may be performed by folding data into the block of the solid state memory.
摘要翻译：提供了一种用于自适应增强后写入读取（EPWR）的系统和方法。可以确定固态存储器块的错误率。当块的确定的错误率比确定的错误率是较高值时的值低的情况下，可以在块上的两个连续增强的后写入读取之间执行折叠。折叠可以通过将数据折叠到固态存储器的块中来执行。

10. 发明授权

US08566671B1 Configurable accelerated post-write read to manage errors 有权
标题翻译：可配置的加速写入后读取来管理错误
公开(公告)号：US08566671B1
公开(公告)日：2013-10-22
申请号：US13538927
申请日：2012-06-29
申请人： Jia Ye , Mrinal Kochar , Jianmin Huang
发明人： Jia Ye , Mrinal Kochar , Jianmin Huang
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C16/00 , G11C29/42 , G11C2029/0409 , G11C2029/0411
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC, where the sample selected depends on the count of erase-program cycles that a block has experienced, where different count ranges can use different samples.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。错误管理在复制到第二部分后提供读取和检查副本。如果副本具有过多的错误位，则在第二或第一部分的不同位置重复该复制。通过只读取样本来读取和检查副本。从具有其自己的ECC的副本的子集中选择样本，其中所选择的样本取决于块经历的擦除 - 编程周期的计数，其中不同的计数范围可以使用不同的样本。

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