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1. 发明申请

US20130107628A1 Selective Word Line Erase In 3D Non-Volatile Memory 有权
公开(公告)号：US20130107628A1
公开(公告)日：2013-05-02
申请号：US13287343
申请日：2011-11-02
申请人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

2. 发明申请

US20130070530A1 HIGH ENDURANCE NON-VOLATILE STORAGE 有权
标题翻译：高耐久性非挥发性储存
公开(公告)号：US20130070530A1
公开(公告)日：2013-03-21
申请号：US13622045
申请日：2012-09-18
申请人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

3. 发明申请

US20110126080A1 DATA CODING FOR IMPROVED ECC EFFICIENCY 有权
标题翻译：数据编码提高ECC效率
公开(公告)号：US20110126080A1
公开(公告)日：2011-05-26
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

4. 发明授权

US07652918B2 Retention margin program verification 有权
标题翻译：保留保证金计划验证
公开(公告)号：US07652918B2
公开(公告)日：2010-01-26
申请号：US11617546
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译：一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。管理电路与所述存储元件阵列通信并执行编程和读取操作。编程操作包括编程多个多状态存储数据。读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

5. 发明申请

US20080311684A1 Programmable Chip Enable and Chip Address in Semiconductor Memory 有权
标题翻译：半导体存储器中的可编程芯片使能和芯片地址
公开(公告)号：US20080311684A1
公开(公告)日：2008-12-18
申请号：US11763287
申请日：2007-06-14
申请人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
发明人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/11524
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

6. 发明申请

US20080158990A1 RETENTION MARGIN PROGRAM VERIFICATION 有权
标题翻译：保留MARGIN程序验证
公开(公告)号：US20080158990A1
公开(公告)日：2008-07-03
申请号：US11617546
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.
摘要翻译：一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。管理电路与所述存储元件阵列通信并执行编程和读取操作。编程操作包括编程多个多状态存储数据。读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

7. 发明申请

US20080158989A1 RETENTION MARGIN PROGRAM VERIFICATION 有权
标题翻译：保留MARGIN程序验证
公开(公告)号：US20080158989A1
公开(公告)日：2008-07-03
申请号：US11617541
申请日：2006-12-28
申请人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
发明人： Jun Wan , Jeffrey W. Lutze , Jian Chen , Yan Li , Alex Mak
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.
摘要翻译：提供了使用部分数据保留余量的存储器件中的数据验证。从区域读取位计数，以确定错误是否会导致内存。在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

8. 发明授权

US08897070B2 Selective word line erase in 3D non-volatile memory 有权
标题翻译： 3D非易失性存储器中的选择性字线擦除
公开(公告)号：US08897070B2
公开(公告)日：2014-11-25
申请号：US13287343
申请日：2011-11-02
申请人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C11/34 , G11C16/04 , G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.
摘要翻译：用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

9. 发明申请

US20140047904A1 VISCOMETER 有权
标题翻译：粘度计
公开(公告)号：US20140047904A1
公开(公告)日：2014-02-20
申请号：US13961394
申请日：2013-08-07
申请人： Alex Mak
发明人： Alex Mak
IPC分类号： G01N11/14
CPC分类号： G01N11/14
摘要： Viscosity or rheology measuring instrument utilizing Hall Effect or like magnetic coupling with parts mounted on driving and driven rotational assemblies.
摘要翻译：使用霍尔效应或类似磁耦合的粘度或流变测量仪器，安装在驱动和驱动旋转组件上。

10. 发明申请

US20080310242A1 SYSTEMS FOR PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY 有权
标题翻译：用于半导体存储器中可编程芯片使能和芯片地址的系统
公开(公告)号：US20080310242A1
公开(公告)日：2008-12-18
申请号：US11763292
申请日：2007-06-14
申请人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
发明人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/88 , G11C5/04
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

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