专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6060375A Process for forming re-entrant geometry for gate electrode of integrated circuit structure 失效
标题翻译：用于形成集成电路结构的栅电极的重入几何的工艺
公开(公告)号：US6060375A
公开(公告)日：2000-05-09
申请号：US690577
申请日：1996-07-31
申请人： Jon Owyang , Sheldon Aronowitz , James P. Kimball
发明人： Jon Owyang , Sheldon Aronowitz , James P. Kimball
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/3215 , H01L29/423 , H01L21/302 , H01L21/425
CPC分类号： H01L21/32155 , H01L21/28114 , H01L21/32137 , H01L29/42376
摘要： A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e., some lying along an X axis in the plane of the masked polysilicon layer on the substrate and others lying along a Y axis in the plane of the masked polysilicon layer on the substrate, the substrate may be rotated 90.degree., rather than 180.degree., between each implantation, and four implantations, rather than two, are performed. After the implantations, the implanted masked polysilicon layer is then subject to an etch, preferably an anisotropic etch, which will remove the unmasked implanted portions of the polysilicon layer, as well as the implanted regions beneath the mask, resulting in a gate electrode with re-entrant or tapered sidewalls, i.e., resembling an inverted trapezoid in cross-section.
摘要翻译：公开了一种具有凹入几何结构的晶体半导体栅电极及其制造方法。新颖的栅电极可以由衬底上的多晶硅层形成，首先将具有中性物质的掩模多晶硅层，即不会将掺杂剂引入到多晶硅中的物质，例如IV族元素，例如硅，或VIII族元素，例如氩气。将中性物质以一定角度注入到掩模多晶硅层中，以提供切割掩模长度（长尺寸）的一侧的锥形注入区域。然后可以将衬底旋转180°，然后再次植入以提供锥形植入区域，其切割掩模长度的相对侧。当具有这样的复数几何形状的栅电极将以其长轴彼此成直角的方式形成在衬底上时，即一些沿着衬底上的被掩膜的多晶硅层的平面中的X轴位于其上，在衬底上的掩模多晶硅层的平面中的Y轴，衬底可以在每次注入之间旋转90度而不是180度，并且执行四次注入而不是两次。在注入后，植入的掩膜多晶硅层然后进行蚀刻，优选是各向异性蚀刻，其将去除多晶硅层的未屏蔽的注入部分以及掩模下面的注入区域，从而形成栅电极入口或锥形侧壁，即横截面类似倒梯形。

2. 发明授权

US06331468B1 Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers 失效
公开(公告)号：US06331468B1
公开(公告)日：2001-12-18
申请号：US09076399
申请日：1998-05-11
申请人： Sheldon Aronowitz , Helmut Puchner , Ravindra A. Kapre , James P. Kimball
发明人： Sheldon Aronowitz , Helmut Puchner , Ravindra A. Kapre , James P. Kimball
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/28202 , H01L21/28247 , H01L29/513 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.

3. 发明授权

US06759337B1 Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate 有权
标题翻译：使用氮等离子体和等离子体在半导体衬底上的集成电路结构上蚀刻可控厚度的氧化物和施加到衬底的rf偏压的工艺
公开(公告)号：US06759337B1
公开(公告)日：2004-07-06
申请号：US09464297
申请日：1999-12-15
申请人： Sheldon Aronowitz , Valeriy Sukharev , John Haywood , James P. Kimball , Helmut Puchner , Ravindra Manohar Kapre , Nicholas Eib
发明人： Sheldon Aronowitz , Valeriy Sukharev , John Haywood , James P. Kimball , Helmut Puchner , Ravindra Manohar Kapre , Nicholas Eib
IPC分类号： H01L21302
CPC分类号： H01L21/31105 , H01L21/28176
摘要： A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.
摘要翻译：公开了一种用于蚀刻氧化物的方法，其中可以通过在蚀刻室中暴露氧化物到氮等离子体，同时将rf偏压施加到半导体衬底上，通过在半导体衬底上预先形成的氧化物的表面，可再现性地精确和均匀的量的氧化硅衬底支撑件，衬底支撑在蚀刻室中。在给定时间段内去除的氧化物的厚度可以通过改变通过衬底支撑件施加到衬底的rf偏置量来改变。

4. 发明授权

US06413881B1 PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NITRIDATION OF UPPER SURFACE OF GATE OF OXIDE TO FORM BARRIER OF NITROGEN ATOMS IN UPPER SURFACE REGION OF GATE OXIDE, AND RESULTING PRODUCT 有权
标题翻译：通过将氧化物的上层表面氧化成形成氮氧化物的上部表面区域的氮化物的氮化物和结果产物来形成具有增强的可靠性的方法
公开(公告)号：US06413881B1
公开(公告)日：2002-07-02
申请号：US09521312
申请日：2000-03-09
申请人： Sheldon Aronowitz , John Haywood , James P. Kimball , Helmut Puchner , Ravindra Manohar Kapre , Nicholas Eib
发明人： Sheldon Aronowitz , John Haywood , James P. Kimball , Helmut Puchner , Ravindra Manohar Kapre , Nicholas Eib
IPC分类号： H01L2131
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L21/3144 , H01L29/518
摘要： A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.
摘要翻译：抑制掺杂剂从栅电极通入薄栅氧化物的方法包括在栅极氧化物上形成栅电极之前，对薄栅极氧化物的上表面进行氮化，从而形成氮原子的势垒栅极氧化物的上表面区域与栅极氧化物和栅电极之间的界面相邻，以在结构退火期间抑制掺杂剂原子从栅电极到薄栅氧化层的通过。在一个实施例中，可以蚀刻硅衬底上的氧化硅的选择性部分，以使用施加到硅衬底的偏压的氮等离子体将氧化物稀释至期望的厚度。然后通过从硅衬底去除偏压，在相同的装置中进行蚀刻的氧化硅的表面的氮化。

5. 发明授权

US06864141B1 Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams 有权
标题翻译：通过激励氮离子束将氮掺入金属硅酸盐基电介质的方法
公开(公告)号：US06864141B1
公开(公告)日：2005-03-08
申请号：US10453118
申请日：2003-06-03
申请人： Wai Lo , James P. Kimball , Verne C. Hornback
发明人： Wai Lo , James P. Kimball , Verne C. Hornback
IPC分类号： H01L21/28 , H01L21/3115 , H01L21/314 , H01L21/8238 , H01L29/51 , H01L21/283 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/823857 , H01L29/518
摘要： A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate.
摘要翻译：制造薄栅极电介质的方法包括在硅衬底上提供金属硅酸盐。将氮气注入到金属硅酸盐中。

6. 发明授权

US06849512B1 Thin gate dielectric for a CMOS transistor and method of fabrication thereof 失效
标题翻译： CMOS晶体管的薄栅极电介质及其制造方法
公开(公告)号：US06849512B1
公开(公告)日：2005-02-01
申请号：US10283630
申请日：2002-10-30
申请人： Wai Lo , James P. Kimball , Verne C. Hornback
发明人： Wai Lo , James P. Kimball , Verne C. Hornback
IPC分类号： H01L21/265 , H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28211 , H01L21/26506 , H01L21/2822 , H01L21/28238 , H01L29/518
摘要： A method of making a thin gate dielectric includes implanting a barrier substance into a region of a silicon substrate. A capacitance-increasing material is implanted into the silicon substrate. An outside layer of the silicon substrate is oxidized to form a first silicon oxide layer. The silicon substrate is oxidized between the first silicon oxide layer and the region.
摘要翻译：制造薄栅极电介质的方法包括将阻挡物质注入到硅衬底的区域中。将电容增加材料注入到硅衬底中。硅衬底的外层被氧化以形成第一氧化硅层。硅衬底在第一氧化硅层和区域之间被氧化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式