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1. 发明授权

US6060375A Process for forming re-entrant geometry for gate electrode of integrated circuit structure 失效
标题翻译：用于形成集成电路结构的栅电极的重入几何的工艺
公开(公告)号：US6060375A
公开(公告)日：2000-05-09
申请号：US690577
申请日：1996-07-31
申请人： Jon Owyang , Sheldon Aronowitz , James P. Kimball
发明人： Jon Owyang , Sheldon Aronowitz , James P. Kimball
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/3215 , H01L29/423 , H01L21/302 , H01L21/425
CPC分类号： H01L21/32155 , H01L21/28114 , H01L21/32137 , H01L29/42376
摘要： A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e., some lying along an X axis in the plane of the masked polysilicon layer on the substrate and others lying along a Y axis in the plane of the masked polysilicon layer on the substrate, the substrate may be rotated 90.degree., rather than 180.degree., between each implantation, and four implantations, rather than two, are performed. After the implantations, the implanted masked polysilicon layer is then subject to an etch, preferably an anisotropic etch, which will remove the unmasked implanted portions of the polysilicon layer, as well as the implanted regions beneath the mask, resulting in a gate electrode with re-entrant or tapered sidewalls, i.e., resembling an inverted trapezoid in cross-section.
摘要翻译：公开了一种具有凹入几何结构的晶体半导体栅电极及其制造方法。新颖的栅电极可以由衬底上的多晶硅层形成，首先将具有中性物质的掩模多晶硅层，即不会将掺杂剂引入到多晶硅中的物质，例如IV族元素，例如硅，或VIII族元素，例如氩气。将中性物质以一定角度注入到掩模多晶硅层中，以提供切割掩模长度（长尺寸）的一侧的锥形注入区域。然后可以将衬底旋转180°，然后再次植入以提供锥形植入区域，其切割掩模长度的相对侧。当具有这样的复数几何形状的栅电极将以其长轴彼此成直角的方式形成在衬底上时，即一些沿着衬底上的被掩膜的多晶硅层的平面中的X轴位于其上，在衬底上的掩模多晶硅层的平面中的Y轴，衬底可以在每次注入之间旋转90度而不是180度，并且执行四次注入而不是两次。在注入后，植入的掩膜多晶硅层然后进行蚀刻，优选是各向异性蚀刻，其将去除多晶硅层的未屏蔽的注入部分以及掩模下面的注入区域，从而形成栅电极入口或锥形侧壁，即横截面类似倒梯形。

2. 发明授权

US5837598A Diffusion barrier for polysilicon gate electrode of MOS device in integrated circuit structure, and method of making same 失效
标题翻译：集成电路结构中MOS器件的多晶硅栅电极的扩散势垒及其制作方法
公开(公告)号：US5837598A
公开(公告)日：1998-11-17
申请号：US816254
申请日：1997-03-13
申请人： Sheldon Aronowitz , Valeriy Sukharev , Jon Owyang , John Haywood
发明人： Sheldon Aronowitz , Valeriy Sukharev , Jon Owyang , John Haywood
IPC分类号： H01L29/78 , H01L21/28 , H01L29/49 , H01L21/425
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e., by implantation followed by furnace annealing, to diffuse and activate the dopant in the polysilicon gate electrode without, however, resulting in penetration of the dopant through the barrier layer into the underlying gate oxide layer or the semiconductor substrate.
摘要翻译：在半导体衬底上形成集成电路结构的一部分的MOS器件的均匀掺杂的多晶硅栅电极通过首先沉积非常薄的非晶或多晶硅层（例如约2nm至约10nm）而形成，栅氧化层。然后将硅层的薄层暴露于由N 2形成的氮等离子体，其功率水平足以破坏硅薄层中的硅 - 硅键，但不足以引起硅的溅射以引起硅的阻挡层并在氮化硅表面形成氮。然后将另外的硅，例如多晶硅沉积在阻挡层上至多晶硅栅电极的期望厚度。然后通常掺杂栅电极，即通过注入然后进行炉退火，以扩散和激活多晶硅栅极电极中的掺杂剂，而不会导致掺杂剂穿过阻挡层进入下面的栅极氧化物层或半导体衬底。

3. 发明申请

US20070031598A1 Method for depositing silicon-containing films 审中-公开
标题翻译：沉积含硅膜的方法
公开(公告)号：US20070031598A1
公开(公告)日：2007-02-08
申请号：US11482782
申请日：2006-07-07
申请人： Yoshikazu Okuyama , Jon Owyang , Helmuth Treichel
发明人： Yoshikazu Okuyama , Jon Owyang , Helmuth Treichel
IPC分类号： C23C16/00
CPC分类号： C23C16/308 , C23C16/345 , C23C16/401 , C23C16/402 , C23C16/45525 , C23C16/45546 , C23C16/45553 , C23C16/45578 , C23C16/4584
摘要： Methods for forming silicon containing films using silylamine moieties are disclosed. In some embodiments, silylamine moieties are employed to deposit silicon-nitrogen, silicon-oxygen, or silicon-nitrogen-oxygen materials at temperatures of less than 550° C. In some embodiments methods are practiced within process chambers adapted to contain a single substrate as well as within process chambers adapted to contain a plurality of substrates, where the silylamine moieties are conveyed to the chambers in across flow type manner.
摘要翻译：公开了使用甲硅烷基部分形成含硅膜的方法。在一些实施方案中，使用甲硅烷基胺部分在低于550℃的温度下沉积硅 - 氮，硅 - 氧或硅 - 氮 - 氧材料。在一些实施方案中，在适于包含单个基材的处理室内实施方法以及在适于容纳多个基底的处理室内，其中甲硅烷基胺部分以跨流动方式输送到室。

4. 发明申请

US20060264066A1 Multilayer multicomponent high-k films and methods for depositing the same 审中-公开
标题翻译：多层多组分高k膜及其沉积方法
公开(公告)号：US20060264066A1
公开(公告)日：2006-11-23
申请号：US11400366
申请日：2006-04-07
申请人： Larry Bartholomew , Helmuth Treichel , Jon Owyang
发明人： Larry Bartholomew , Helmuth Treichel , Jon Owyang
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L21/3142 , C23C16/308 , C23C16/45523 , H01L21/0214 , H01L21/02145 , H01L21/02148 , H01L21/02153 , H01L21/02161 , H01L21/0217 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/02194 , H01L21/02266 , H01L21/0228 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/3145 , H01L21/31604 , H01L21/31608 , H01L21/31637 , H01L21/31645 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention provides systems and methods for forming a multi-layer, multi-component high-k dielectric film. In some embodiments, the present invention provides systems and methods for forming high-k dielectric films that comprise hafnium, titanium, oxygen, nitrogen, and other components. In a further aspect of the present invention, the dielectric films are formed having composition gradients.
摘要翻译：本发明提供了用于形成多层多组分高k电介质膜的系统和方法。在一些实施方案中，本发明提供用于形成包含铪，钛，氧，氮和其它组分的高k电介质膜的系统和方法。在本发明的另一方面，形成具有组成梯度的电介质膜。

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