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    • 1. 发明授权
    • Side tables annotating an instruction stream
    • 侧表注释指令流
    • US07069421B1
    • 2006-06-27
    • US09429094
    • 1999-10-28
    • John S. Yates, Jr.David L. ReesePaul H. HohenseeKorbin S. Van DykeT. R. Ramesh
    • John S. Yates, Jr.David L. ReesePaul H. HohenseeKorbin S. Van DykeT. R. Ramesh
    • G06F9/30
    • G06F9/45533
    • A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.
    • 微处理器芯片,以及用于该微处理器芯片的方法。 该芯片具有指令流水线电路和地址转换电路。 表查找电路索引到表中,该表具有与由地址转换电路翻译的每个相应地址范围相关联的条目。 该表的每个条目描述存在位于相应的相应地址范围内的指令的替代编码的可能性。 表查找电路检索对应于该地址的表条目,并可作为执行在计算机上执行的非主管模式程序的指令的基本指令周期的一部分。 中断电路与指令流水线电路协同设计,以至少部分地基于计算机的存储状态和指令的地址同步地触发执行过程指令的中断,指令的架构定义不是 要求中断。 用于中断的处理程序响应于表的内容,以影响指令流水线电路,以基于与该指令相关联的表条目的内容来实现对结构上可视数据操纵行为的控制或指令的控制传递行为。
    • 3. 发明申请
    • Computer with two execution modes
    • 具有两种执行模式的计算机
    • US20090204785A1
    • 2009-08-13
    • US11982419
    • 2007-10-31
    • John S. Yates, JR.David L. ReeseKorbin S. Van DykeT. R. RameshPaul H. Hohensee
    • John S. Yates, JR.David L. ReeseKorbin S. Van DykeT. R. RameshPaul H. Hohensee
    • G06F9/30G06F12/10
    • G06F9/30189G06F9/30174G06F9/30196G06F9/3802
    • A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
    • 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令,存储器被划分为页面以供虚拟存储器管理器管理,存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行,并且获取存储的指示符元素,其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示,在该约定下,相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线识别来自第一页面的执行流程,其相关联的指示符元素指示第一架构。 或执行约定,到第二页,其相关联的指示符元素指示第一个架构或执行约定。 响应于识别,处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。
    • 5. 发明授权
    • Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
    • 用于执行两个指令集的计算机,并添加一个宏指令结束标记,用于在循环终止后执行迭代
    • US07941647B2
    • 2011-05-10
    • US11982419
    • 2007-10-31
    • John S. Yates, Jr.David L. ReeseKorbin S. Van DykeT. R. RameshPaul H. Hohensee
    • John S. Yates, Jr.David L. ReeseKorbin S. Van DykeT. R. RameshPaul H. Hohensee
    • G06F9/22
    • G06F9/30189G06F9/30174G06F9/30196G06F9/3802
    • A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page.
    • 一台电脑。 处理器流水线交替执行针对第一和第二不同计算机体系结构编码的编码或编码以执行第一和第二不同处理惯例的指令。 存储器存储由处理器流水线执行的指令,存储器被划分为页面以供虚拟存储器管理器管理,存储器的单个地址空间具有第一和第二页面。 存储器单元从存储器中取出指令以由流水线执行,并且获取存储的指示符元素,其与要获取指令的单个地址空间的相应存储器页相关联。 每个指示符元素被设计为存储两个不同的计算机体系结构和/或执行约定中的哪一个的指示,在该约定下,相关联的页面的指令数据将由处理器管线执行。 存储器单元和/或处理器流水线将来自第一页面的执行流程(其相关联的指示符元素指示第一架构或执行约定)识别到第二页面,其第二页面的相关联的指示符元素指示第一个架构或执行约定。 响应于识别,处理器流水线的处理模式或存储器的存储内容适应于执行由该指令页面所对应的指标元素所指示的体系结构和/或规定的指令。
    • 7. 发明授权
    • Variable length instruction alignment device and method
    • 可变长度指令对齐装置及方法
    • US06654872B1
    • 2003-11-25
    • US09490888
    • 2000-01-27
    • T. R. RameshKorbin S. Van Dyke
    • T. R. RameshKorbin S. Van Dyke
    • G06F9315
    • G06F9/3816G06F9/30149
    • An instruction aligner and method evaluates a fixed length instruction cache line by breaking it into at least two components. These two components, in one embodiment, include half of the instruction cache line being designated as most significant bytes and the second half of the instruction cache line being designated as least significant bytes. A byte right rotator is responsible for feeding the next sixteen bytes of the instruction stream, while a byte right shifter shifts the unused bytes of the current sixteen bytes the aligner is working on. The byte rotator and byte shifter combine to provide aligned variable length instructions for decoding based on either a fetch PC value or current instruction length.
    • 指令对齐器和方法通过将固定长度的指令高速缓存行分解成至少两个组件来评估它。 在一个实施例中,这两个组件包括指定高速缓存行的一半被指定为最高有效字节,指令高速缓存行的后半部分被指定为最低有效字节。 一个字节右旋转器负责馈送指令流的下一个十六个字节,而一个字节右移位器移位对准器正在工作的当前十六个字节的未使用字节。 字节转换器和字节移位器组合以提供对准的可变长度指令,用于基于获取的PC值或当前指令长度进行解码。
    • 8. 发明授权
    • Exception mechanism for a computer
    • US06934832B1
    • 2005-08-23
    • US09667226
    • 2000-09-21
    • Korbin S. Van DykePaul CampbellShalesh ThusooT. R. RameshAlan McNaughton
    • Korbin S. Van DykePaul CampbellShalesh ThusooT. R. RameshAlan McNaughton
    • G06F11/00
    • G06F9/30174G06F9/3851G06F9/3861
    • A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by user-state programs stored in a main memory of the computer, the instruction set having variable-length instructions and many instructions having multiple side-effects and a potential to raise multiple exceptions, (b) for at least some instructions of the complex instruction set, to issue two or more instructions in a second internal form into the execution pipeline; (c) to generate information descriptive of instructions to be executed by the pipeline, and to store the information into non-pipelined processor registers of the computer; and (d) to determine whether instructions will complete in the pipeline, and to abstain from writing descriptive information into the processor registers for instructions following an instruction determined not to complete. The pipeline exception circuitry is designed to recognize an exception occurring in an instruction after a first side-effect of the instruction has been architecturally committed, and thereupon, to architecturally expose in the processor registers information describing a processor state of the computer, including an intra-instruction program counter value, and to transfer execution to an exception handler. Pipeline resumption circuitry is effective, after completion of the software exception handler, to resume execution of the excepted program based on the information in the processor registers. The processor registers of the computer are designed to architecturally expose sufficient information about the state of the excepted instruction that the transfer and resume are effected without saving processor state to the main memory, the processor registers and general purpose registers of the computer together providing sufficient working storage for execution of the exception handler and resumption of the program, without storing processor state to the main memory.