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1. 发明授权

US06797620B2 Method and apparatus for improved electroplating fill of an aperture 失效
标题翻译：用于改善孔的电镀填充物的方法和装置
公开(公告)号：US06797620B2
公开(公告)日：2004-09-28
申请号：US10124095
申请日：2002-04-16
申请人： John S. Lewis , Srinivas Gandikota , Sivakami Ramanathan , Girish Dixit , Robin Cheung , Fusen Chen
发明人： John S. Lewis , Srinivas Gandikota , Sivakami Ramanathan , Girish Dixit , Robin Cheung , Fusen Chen
IPC分类号： H01L2144
CPC分类号： H01L21/2855 , H01L21/76879
摘要： A method and apparatus is provided for filling apertures formed in a substrate surface by depositing materials that selectively inhibit or limit the formation or growth of subsequent layers used to fill an aperture. In one aspect, a method is provided for processing a substrate including providing a substrate having a field and apertures formed therein, wherein the apertures each have a bottom and sidewalls, depositing a seed layer on the bottom and sidewalls of the apertures, depositing a growth-inhibiting layer on at least one of the field of the substrate or an upper portion of the sidewalls of the apertures, and depositing a conductive layer on the growth-inhibiting layer and the seed layer. Deposition of the growth-inhibiting layer improves fill of the aperture from the bottom of the aperture up to the field of the substrate.
摘要翻译：提供了一种方法和装置，用于通过沉积选择性地抑制或限制用于填充孔的后续层的形成或生长的材料来填充形成在衬底表面中的孔。在一个方面，提供了一种用于处理衬底的方法，包括提供具有形成在其中的场和孔的衬底，其中每个孔具有底部和侧壁，在孔的底部和侧壁上沉积种子层，沉积生长在衬底的场中的至少一个或孔的侧壁的上部中的至少一个上的抑制层，并且在生长抑制层和种子层上沉积导电层。生长抑制层的沉积改善了孔的填充，从孔的底部到基底的场。

2. 发明授权

US06905622B2 Electroless deposition method 有权
公开(公告)号：US06905622B2
公开(公告)日：2005-06-14
申请号：US10117712
申请日：2002-04-03
申请人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
发明人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
IPC分类号： C23C18/16 , H01L21/02 , H01L21/285 , H01L21/288 , H01L21/306 , H01L21/321 , H01L21/768 , B44C1/22 , B05D3/04 , B05D3/10
CPC分类号： H01L21/02074 , C23C18/1694 , C23C18/1831 , C23C18/1834 , C23C18/1851 , C23C18/1879 , C23C18/1882 , C23C18/1893 , C23C18/31 , C23C18/34 , C23C18/36 , C23C18/50 , H01L21/02068 , H01L21/28518 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76874 , H01L2221/1089
摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.

3. 发明授权

US06899816B2 Electroless deposition method 有权
标题翻译：无电沉积法
公开(公告)号：US06899816B2
公开(公告)日：2005-05-31
申请号：US10117711
申请日：2002-04-03
申请人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
发明人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
IPC分类号： C23C18/18 , H01L21/285 , H01L21/288 , H01L21/336 , H01L21/768 , B44C1/22 , B05D3/04 , B05D3/10
CPC分类号： H01L21/76843 , C23C18/1651 , C23C18/1893 , H01L21/28518 , H01L21/288 , H01L21/76849 , H01L21/76874 , H01L29/665 , H01L2221/1089
摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.
摘要翻译：提供了通过无电沉积技术形成金属或金属硅化物层的方法和装置。在一个方面，提供了一种用于处理衬底的方法，包括在衬底表面上沉积起始层，清洁衬底表面，以及通过将引发层暴露于无电镀溶液而在引发层上沉积导电材料。该方法可以进一步包括用酸性溶液蚀刻衬底表面并在沉积起始层之前清洁酸性溶液的衬底。起始层可以通过将基材表面暴露于贵金属化学电解溶液或含硼烷溶液来形成。导电材料可以用含硼烷的还原剂沉积。导电材料可以用作钝化层，阻挡层，种子层，或用于形成金属硅化物层。

4. 发明申请

US20050136185A1 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application 审中-公开
标题翻译：后冲洗以改善无电钴在铜上的选择性沉积，用于ULSI应用
公开(公告)号：US20050136185A1
公开(公告)日：2005-06-23
申请号：US10979078
申请日：2004-10-29
申请人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish Dixit
发明人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish Dixit
IPC分类号： B05D1/40 , B05D3/00 , C23C18/16 , C23C18/31 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/302 , H01L21/31 , H01L21/44 , H01L21/461 , H01L21/768
CPC分类号： H01L21/76877 , C23C18/166 , C23C18/1831 , C23C18/1834 , C23C18/1879 , C23C18/1882 , C23C18/34 , C23C18/36 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/76814 , H01L21/76849 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76883
摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.
摘要翻译：提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用酸性溶液。在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。

5. 发明授权

US06824666B2 Electroless deposition method over sub-micron apertures 有权
标题翻译：亚微米孔径上的无电沉积方法
公开(公告)号：US06824666B2
公开(公告)日：2004-11-30
申请号：US10059822
申请日：2002-01-28
申请人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Muhammad Atif Malik , Sivakami Ramanathan , Girish A. Dixit , Robin Cheung
发明人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Muhammad Atif Malik , Sivakami Ramanathan , Girish A. Dixit , Robin Cheung
IPC分类号： C23C2800
CPC分类号： H01L21/76843 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1831 , C23C18/28 , C23C18/30 , C23C18/38 , H01L21/288 , H01L21/2885 , H01L21/6708 , H01L21/76864 , H01L21/76868 , H01L21/76871 , H01L21/76874 , H01L21/76877 , H01L2221/1089 , Y10S428/936
摘要： An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.
摘要翻译：一种沉积包含至少一种选自贵金属，半贵金属，其合金及其组合的金属的催化剂层的装置和方法，其形成在基板上形成的亚微米特征。贵金属的实例包括钯和铂。半贵金属的实例包括钴，镍和钨。可通过无电沉积，电镀或化学气相沉积来沉积催化层。在一个实施方案中，催化层可以沉积在特征中以用作随后沉积的导电材料的阻挡层。在另一个实施方案中，催化剂层可以沉积在阻挡层上。在另一个实施方案中，催化层可以沉积在沉积在阻挡层上的种子层上，以充当种子层中任何不连续性的“贴片”。一旦沉积了催化层，可以在催化剂层上沉积诸如铜的导电材料。在一个实施例中，导电材料通过无电沉积沉积在催化剂层上。在另一个实施方案中，导电材料通过无电沉积然后电镀或随后进行化学气相沉积沉积在催化剂层上。在另一个实施例中，导电材料通过电镀或化学气相沉积沉积在催化层上。

6. 发明授权

US06821909B2 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application 失效
标题翻译：后冲洗以改善无电钴在铜上的选择性沉积，用于ULSI应用
公开(公告)号：US06821909B2
公开(公告)日：2004-11-23
申请号：US10284855
申请日：2002-10-30
申请人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
发明人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
IPC分类号： H01L2131
CPC分类号： H01L21/76877 , C23C18/166 , C23C18/1831 , C23C18/1834 , C23C18/1879 , C23C18/1882 , C23C18/34 , C23C18/36 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/76814 , H01L21/76849 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76883
摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.
摘要翻译：提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用酸性溶液。在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。

7. 发明授权

US06878245B2 Method and apparatus for reducing organic depletion during non-processing time periods 失效
标题翻译：在非处理时间段内减少有机物耗尽的方法和装置
公开(公告)号：US06878245B2
公开(公告)日：2005-04-12
申请号：US10085338
申请日：2002-02-27
申请人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Sivakami Ramanathan , Muhammad Atif Malik , Girish A. Dixit
发明人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Sivakami Ramanathan , Muhammad Atif Malik , Girish A. Dixit
IPC分类号： C25D21/14 , C25D21/18 , C25D17/00 , C25D21/00
CPC分类号： C25D21/18 , C25D21/14
摘要： Embodiments of the invention generally provide an apparatus and method for replenishing organic molecules in an electroplating bath. The replenishment process of the present invention may occur on a real-time basis, and therefore, the concentration of organics minimally varies from desired concentration levels. The replenishment method generally includes conducting pre-processing depletion measurements in order to determine organic depletion rates per current density applied in the electroplating system. Once the organic depletion rates per current density are determined, these depletion rates may be applied to an electroplating processing recipe to calculate the volume of organic depletion per recipe step. The calculated volume of organic depletion per recipe step may then be used to determine the volume of organic molecule replenishment per unit of time that is required per recipe step in order to maintain a desired concentration of organics in the plating solution. The calculated replenishment volume may then be added to the processing recipe so that the replenishment process may occur at real-time during processing periods. The apparatus generally includes a selectively actuated valve in communicaiton with a fluid delivery line, wherein the valve is configured to fluidly isolate a plating cell during a non-processing time period. The valve may be controlled by a system controller, and thus, the fluid level in the cell may be controlled during a non-processing time period.
摘要翻译：本发明的实施方案通常提供用于在电镀浴中补充有机分子的装置和方法。本发明的补充方法可以在实时的基础上进行，因此有机物的浓度最小化从期望的浓度水平变化。补充方法通常包括进行预处理耗尽测量，以便确定在电镀系统中施加的每个电流密度的有机耗尽率。一旦确定了每个电流密度的有机耗尽率，则这些耗尽率可以应用于电镀处理配方以计算每个配方步骤的有机耗尽量。然后可以使用每个配方步骤的计算的有机耗尽体积来确定每个配方步骤所需的每单位时间的有机分子补充体积，以维持电镀溶液中所需的有机物浓度。计算的补充量然后可以被添加到处理配方中，使得补货过程可以在处理时段期间实时发生。该装置通常包括与流体输送管线通信的选择性致动的阀，其中阀被配置为在非处理时间段期间流体地隔离电镀槽。阀可以由系统控制器控制，因此，可以在非处理时间段期间控制单元中的液位。

8. 发明申请

US20070082477A1 Integrated circuit fabricating techniques employing sacrificial liners 审中-公开
标题翻译：采用牺牲衬垫的集成电路制造技术
公开(公告)号：US20070082477A1
公开(公告)日：2007-04-12
申请号：US11245712
申请日：2005-10-06
申请人： Mehul Naik , Srinivas Gandikota , Girish Dixit , Dennis Yost
发明人： Mehul Naik , Srinivas Gandikota , Girish Dixit , Dennis Yost
IPC分类号： H01L21/4763 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/76808 , H01L21/76877
摘要： The present invention provides techniques for fabricating integrated circuit structures in semiconductor wafer fabrication. A via hole is prepared in a dielectric stack having a bottom via etch stop layer. The via hole is not extended through the via etch stop layer at this stage of the process. The via hole is partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the via hole. A substantially conformal sacrificial layer is deposited on the top surface of the dielectric stack and in the recess. Then, a photoresist layer is deposited on the sacrificial fill. A trench etch mask overlaying the via hole, is developed in the photoresist layer. This mask is etched through the sacrificial layer that is formed on the top surface of the dielectric stack as well as through the sacrificial fill and sacrificial layer that is present in the via hole. Additionally, the mask is employed for etching a trench partly through the dielectric layer thereby forming a trench and an underlying via hole. The via hole is then extended through the via etch stop layer. Subsequently, the photoresist layer and the sacrificial layer are removed from the top surface of the dielectric stack resulting in a trench and underlying via hole that is suitable for fabricating a dual damascene structure. Alternatively, a recess can be formed by depositing a substantially conformal sacrificial layer on the top surface of the dielectric stack and in the via hole to form a lined via hole. The lined via hole is then partly filled with a sacrificial via fill such that a recess without sacrificial via fill is formed in the top portion of the lined via hole. Next, a photoresist layer is deposited in the recess and on the sacrificial liner that is deposited on the top surface of the dielectric stack.
摘要翻译：本发明提供了在半导体晶片制造中制造集成电路结构的技术。在具有底部通孔蚀刻停止层的电介质叠层中制备通孔。在该过程的这个阶段，通孔不延伸穿过通孔蚀刻停止层。通孔部分地填充有牺牲通孔填充物，使得在通孔的顶部部分中形成没有牺牲通孔填充物的凹部。基本上共形的牺牲层沉积在电介质叠层的顶表面和凹槽中。然后，在牺牲填充物上沉积光致抗蚀剂层。在光致抗蚀剂层中显影覆盖通孔的沟槽蚀刻掩模。该掩模通过形成在电介质堆叠的顶表面上的牺牲层以及穿过存在于通孔中的牺牲填充层和牺牲层进行蚀刻。此外，掩模用于部分地通过介电层蚀刻沟槽，从而形成沟槽和下面的通孔。然后通孔穿过通孔蚀刻停止层。随后，从电介质堆叠的顶表面去除光致抗蚀剂层和牺牲层，产生适于制造双镶嵌结构的沟槽和下面的通孔。或者，可以通过在电介质堆叠的顶表面上和通孔中沉积基本上共形的牺牲层来形成凹槽，以形成衬里的通孔。然后将衬里的通孔部分地填充有牺牲通孔填充物，使得在衬里通孔的顶部部分中形成没有牺牲通孔填充物的凹部。接下来，将光致抗蚀剂层沉积在沉积在电介质堆叠的顶表面上的凹部和牺牲衬垫上。

9. 发明授权

US09330939B2 Method of enabling seamless cobalt gap-fill 有权
标题翻译：实现无缝钴填隙的方法
公开(公告)号：US09330939B2
公开(公告)日：2016-05-03
申请号：US13786644
申请日：2013-03-06
申请人： Bhushan N. Zope , Avgerinos V. Gelatos , Bo Zheng , Yu Lei , Xinyu Fu , Srinivas Gandikota , Sang-Ho Yu , Mathew Abraham
发明人： Bhushan N. Zope , Avgerinos V. Gelatos , Bo Zheng , Yu Lei , Xinyu Fu , Srinivas Gandikota , Sang-Ho Yu , Mathew Abraham
IPC分类号： H01L21/76 , H01L21/48 , H01L21/02 , H01L21/768 , H01L21/285
CPC分类号： H01L21/76879 , H01L21/02057 , H01L21/2855 , H01L21/28556 , H01L21/4846 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76877 , H01L21/76883 , H01L23/53209 , H01L23/5329 , H01L29/66621
摘要： Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.
摘要翻译：提供了在半导体器件的接触结构中沉积接触金属层的方法。在一个实施例中，提供了一种在半导体器件中沉积用于形成接触结构的接触金属层的方法。该方法包括进行循环金属沉积工艺，以将接触金属层沉积在衬底上并退火设置在衬底上的接触金属层。循环金属沉积工艺包括将衬底暴露于沉积前体气体混合物以将接触金属层的一部分沉积在衬底上，将接触金属层的该部分暴露于等离子体处理工艺，并重复将衬底暴露于沉积前体气体混合物，并将接触金属层的部分暴露于等离子体处理工艺，直到实现接触金属层的预定厚度。

10. 发明申请

US20140017408A1 Deposition Of N-Metal Films Comprising Aluminum Alloys 有权
标题翻译：包含铝合金的N-金属膜的沉积
公开(公告)号：US20140017408A1
公开(公告)日：2014-01-16
申请号：US13930194
申请日：2013-06-28
申请人： Srinivas Gandikota , Xinliang Lu , Shih Chung Chen , Wei Tang , Jing Zhou , Seshadri Ganguli , David Thompson , Jeffrey W. Anthis , Atif Noori , Faruk Gungor , Dien-Yeh Wu , Mei Chang , Xinyu Fu , Yu Lei
发明人： Srinivas Gandikota , Xinliang Lu , Shih Chung Chen , Wei Tang , Jing Zhou , Seshadri Ganguli , David Thompson , Jeffrey W. Anthis , Atif Noori , Faruk Gungor , Dien-Yeh Wu , Mei Chang , Xinyu Fu , Yu Lei
IPC分类号： C23C18/00
CPC分类号： C23C18/00 , C23C16/08 , C23C16/18 , C23C16/45527 , C23C16/45534 , C23C16/45553
摘要： Provided are methods of depositing films comprising alloys of aluminum, which may be suitable as N-metal films. Certain methods comprise exposing a substrate surface to a metal halide precursor comprising a metal halide selected from TiCl4, TaCl5 and HfCl4 to provide a metal halide at the substrate surface; purging metal halide; exposing the substrate surface to an alkyl aluminum precursor comprising one or more of dimethyaluminum hydride, diethylhydridoaluminum, methyldihydroaluminum, and an alkyl aluminum hydrides of the formula [(CxHy)3-aAlHa]n, wherein x has a value of 1 to 3, y has a value of 2x+2, a has a value of 1 to 2, and n has a value of 1 to 4; and exposing the substrate surface to an alane-containing precursor comprising one or more of dimethylethylamine alane, methylpyrrolidinealane, di(methylpyrolidine)alane, and trimethyl amine alane borane. Other methods comprise exposing a substrate surface to a metal precursor and trimethyl amine alane borane.
摘要翻译：提供了沉积包括铝合金的膜的方法，其可以适合作为N-金属膜。某些方法包括将衬底表面暴露于包含选自TiCl 4，TaCl 5和HfCl 4的金属卤化物的金属卤化物前体，以在衬底表面提供金属卤化物; 清洗金属卤化物; 将基材表面暴露于包含一种或多种二氢化铝氢化物，二乙基氢化铝，甲基二氢铝和式[（C x H y）3-a AlHa] n的烷基铝氢化物的烷基铝前体，其中x具有1至3的值，y 具有2x + 2的值，a具有1至2的值，并且n具有1至4的值; 并将基材表面暴露于含有二甲基乙基胺丙烷，甲基吡咯烷烃，二（甲基吡咯烷）甲烷和三甲基胺丙烷硼烷中的一种或多种的含Alane的前体。其他方法包括将基底表面暴露于金属前体和三甲基胺丙烷硼烷。

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