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1. 发明授权

US06824666B2 Electroless deposition method over sub-micron apertures 有权
标题翻译：亚微米孔径上的无电沉积方法
公开(公告)号：US06824666B2
公开(公告)日：2004-11-30
申请号：US10059822
申请日：2002-01-28
申请人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Muhammad Atif Malik , Sivakami Ramanathan , Girish A. Dixit , Robin Cheung
发明人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Muhammad Atif Malik , Sivakami Ramanathan , Girish A. Dixit , Robin Cheung
IPC分类号： C23C2800
CPC分类号： H01L21/76843 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1831 , C23C18/28 , C23C18/30 , C23C18/38 , H01L21/288 , H01L21/2885 , H01L21/6708 , H01L21/76864 , H01L21/76868 , H01L21/76871 , H01L21/76874 , H01L21/76877 , H01L2221/1089 , Y10S428/936
摘要： An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.
摘要翻译：一种沉积包含至少一种选自贵金属，半贵金属，其合金及其组合的金属的催化剂层的装置和方法，其形成在基板上形成的亚微米特征。贵金属的实例包括钯和铂。半贵金属的实例包括钴，镍和钨。可通过无电沉积，电镀或化学气相沉积来沉积催化层。在一个实施方案中，催化层可以沉积在特征中以用作随后沉积的导电材料的阻挡层。在另一个实施方案中，催化剂层可以沉积在阻挡层上。在另一个实施方案中，催化层可以沉积在沉积在阻挡层上的种子层上，以充当种子层中任何不连续性的“贴片”。一旦沉积了催化层，可以在催化剂层上沉积诸如铜的导电材料。在一个实施例中，导电材料通过无电沉积沉积在催化剂层上。在另一个实施方案中，导电材料通过无电沉积然后电镀或随后进行化学气相沉积沉积在催化剂层上。在另一个实施例中，导电材料通过电镀或化学气相沉积沉积在催化层上。

2. 发明授权

US06878245B2 Method and apparatus for reducing organic depletion during non-processing time periods 失效
标题翻译：在非处理时间段内减少有机物耗尽的方法和装置
公开(公告)号：US06878245B2
公开(公告)日：2005-04-12
申请号：US10085338
申请日：2002-02-27
申请人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Sivakami Ramanathan , Muhammad Atif Malik , Girish A. Dixit
发明人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Sivakami Ramanathan , Muhammad Atif Malik , Girish A. Dixit
IPC分类号： C25D21/14 , C25D21/18 , C25D17/00 , C25D21/00
CPC分类号： C25D21/18 , C25D21/14
摘要： Embodiments of the invention generally provide an apparatus and method for replenishing organic molecules in an electroplating bath. The replenishment process of the present invention may occur on a real-time basis, and therefore, the concentration of organics minimally varies from desired concentration levels. The replenishment method generally includes conducting pre-processing depletion measurements in order to determine organic depletion rates per current density applied in the electroplating system. Once the organic depletion rates per current density are determined, these depletion rates may be applied to an electroplating processing recipe to calculate the volume of organic depletion per recipe step. The calculated volume of organic depletion per recipe step may then be used to determine the volume of organic molecule replenishment per unit of time that is required per recipe step in order to maintain a desired concentration of organics in the plating solution. The calculated replenishment volume may then be added to the processing recipe so that the replenishment process may occur at real-time during processing periods. The apparatus generally includes a selectively actuated valve in communicaiton with a fluid delivery line, wherein the valve is configured to fluidly isolate a plating cell during a non-processing time period. The valve may be controlled by a system controller, and thus, the fluid level in the cell may be controlled during a non-processing time period.
摘要翻译：本发明的实施方案通常提供用于在电镀浴中补充有机分子的装置和方法。本发明的补充方法可以在实时的基础上进行，因此有机物的浓度最小化从期望的浓度水平变化。补充方法通常包括进行预处理耗尽测量，以便确定在电镀系统中施加的每个电流密度的有机耗尽率。一旦确定了每个电流密度的有机耗尽率，则这些耗尽率可以应用于电镀处理配方以计算每个配方步骤的有机耗尽量。然后可以使用每个配方步骤的计算的有机耗尽体积来确定每个配方步骤所需的每单位时间的有机分子补充体积，以维持电镀溶液中所需的有机物浓度。计算的补充量然后可以被添加到处理配方中，使得补货过程可以在处理时段期间实时发生。该装置通常包括与流体输送管线通信的选择性致动的阀，其中阀被配置为在非处理时间段期间流体地隔离电镀槽。阀可以由系统控制器控制，因此，可以在非处理时间段期间控制单元中的液位。

3. 发明授权

US06821909B2 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application 失效
标题翻译：后冲洗以改善无电钴在铜上的选择性沉积，用于ULSI应用
公开(公告)号：US06821909B2
公开(公告)日：2004-11-23
申请号：US10284855
申请日：2002-10-30
申请人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
发明人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
IPC分类号： H01L2131
CPC分类号： H01L21/76877 , C23C18/166 , C23C18/1831 , C23C18/1834 , C23C18/1879 , C23C18/1882 , C23C18/34 , C23C18/36 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/76814 , H01L21/76849 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76883
摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.
摘要翻译：提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用酸性溶液。在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。

4. 发明授权

US07205228B2 Selective metal encapsulation schemes 失效
标题翻译：选择性金属封装方案
公开(公告)号：US07205228B2
公开(公告)日：2007-04-17
申请号：US10812480
申请日：2004-03-30
申请人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
发明人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/76829 , H01L21/7685 , H01L21/76885
摘要： A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.
摘要翻译：在一个或多个实施例中，处理半导体衬底的方法和系统包括在衬底表面上沉积保护层，所述保护层包括布置在电介质材料中的导电元件; 处理所述保护层以暴露所述导电元件; 将金属钝化层无电沉积到导电元件上; 以及在无电沉积之后从衬底去除保护层的至少一部分。在另一方面，一种处理半导体的方法和系统包括在包括导电元件的衬底表面上沉积金属钝化层，掩蔽钝化层以保护衬底表面的下面的导电元件，去除未屏蔽的钝化层，以及去除掩模从钝化层。

5. 发明授权

US06951599B2 Electropolishing of metallic interconnects 失效
标题翻译：电抛光金属互连
公开(公告)号：US06951599B2
公开(公告)日：2005-10-04
申请号：US10188163
申请日：2002-07-01
申请人： Joseph Yahalom , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
发明人： Joseph Yahalom , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
IPC分类号： C25F3/16 , C25F3/22 , C25F7/00
CPC分类号： C25F3/16 , C25F3/22
摘要： Embodiments of the present invention generally relate to a method and apparatus for planarizing a substrate by electropolishing techniques. Certain embodiments of an electropolishing apparatus include a contact ring adapted to support a substrate, a cell body adapted to hold an electropolishing solution, a fluid supply system adapted to provide the electropolishing solution to the cell body, a cathode disposed within the cell body, a power supply system in electrical communication with the contact ring and the cathode, and a controller coupled to at least the fluid supply system and the power supply system. The controller may be adapted to provide a first set of electropolishing conditions to form a boundary layer between the substrate and the electropolishing solution to an initial thickness and may be adapted to provide a second set of electropolishing conditions to control the boundary layer to a subsequent thickness less than or equal to the initial thickness.
摘要翻译：本发明的实施例一般涉及通过电抛光技术来平坦化衬底的方法和装置。电抛光装置的某些实施例包括适于支撑基底的接触环，适于保持电解抛光溶液的电池体，适于将电解抛光溶液提供给电池体的流体供应系统，设置在电池体内的阴极，电源系统与接触环和阴极电连通，以及控制器，耦合到至少流体供应系统和电源系统。控制器可以适于提供第一组电抛光条件，以在衬底和电解抛光溶液之间形成初始厚度的边界层，并且可适于提供第二组电抛光条件以将边界层控制到随后的厚度小于或等于初始厚度。

6. 发明授权

US07425716B2 Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to a large area electron beam 失效
标题翻译：用于在暴露于大面积电子束之后降低电介质涂覆的基底上的电荷密度的方法和装置
公开(公告)号：US07425716B2
公开(公告)日：2008-09-16
申请号：US11414649
申请日：2006-04-27
申请人： Alexandros T. Demos , Khaled A. Elsheref , Yuri Trachuk , Tom K. Cho , Girish A. Dixit , Hichem M'Saad , Derek Witty
发明人： Alexandros T. Demos , Khaled A. Elsheref , Yuri Trachuk , Tom K. Cho , Girish A. Dixit , Hichem M'Saad , Derek Witty
IPC分类号： H02H23/00
CPC分类号： H01J37/317 , H01J2237/0041
摘要： Embodiments in accordance with the present invention relate to a number of techniques, which may be applied alone or in combination, to reduce charge damage of substrates exposed to electron beam radiation. In one embodiment, charge damage is reduced by establishing a robust electrical connection between the exposed substrate and ground. In another embodiment, charge damage is reduced by modifying the sequence of steps for activating and deactivating the electron beam source to reduce the accumulation of charge on the substrate. In still another embodiment, a plasma is struck in the chamber containing the e-beam treated substrate, thereby removing accumulated charge from the substrate. In a further embodiment of the present invention, the voltage of the anode of the e-beam source is reduced in magnitude to account for differences in electron conversion efficiency exhibited by different cathode materials.
摘要翻译：根据本发明的实施例涉及可以单独或组合应用的多种技术，以减少暴露于电子束辐射的衬底的电荷损伤。在一个实施例中，通过在暴露的基板和地之间建立牢固的电连接来减小电荷损伤。在另一个实施例中，通过修改用于激活和去激活电子束源的步骤顺序来减少电荷损伤，以减少电荷在衬底上的累积。在另一个实施例中，在包含电子束处理的衬底的室中撞击等离子体，从而从衬底去除积聚的电荷。在本发明的另一个实施例中，电子束源的阳极的电压的大小被减小以考虑到由不同的阴极材料表现的电子转换效率的差异。

7. 发明授权

US07018941B2 Post treatment of low k dielectric films 有权
标题翻译：后处理低k电介质膜
公开(公告)号：US07018941B2
公开(公告)日：2006-03-28
申请号：US10830203
申请日：2004-04-21
申请人： Zhenjiang Cui , Josephine J. Chang , Alexandros T. Demos , Reza Arghavani , Derek R. Witty , Helen R. Armer , Girish A. Dixit , Hichem M'Saad
发明人： Zhenjiang Cui , Josephine J. Chang , Alexandros T. Demos , Reza Arghavani , Derek R. Witty , Helen R. Armer , Girish A. Dixit , Hichem M'Saad
IPC分类号： H01L21/31 , H01L21/461
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/02351
摘要： A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling the low dielectric constant film such that the low dielectric constant film is exposed to the desired high temperature for about five seconds or less. In one aspect, the post-treatment also includes exposing the low dielectric constant film to an electron beam treatment and/or UV radiation.
摘要翻译：提供了一种在衬底上沉积低介电常数膜并对低介电常数膜进行后处理的方法。后处理包括将低介电常数膜快速加热到期望的高温，然后快速冷却低介电常数膜，使得低介电常数膜暴露于所需的高温约5秒或更短。一方面，后处理还包括将低介电常数膜暴露于电子束处理和/或UV辐射。

8. 发明授权

US06962883B2 Integrated circuit insulator and method 失效
标题翻译：集成电路绝缘子及方法
公开(公告)号：US06962883B2
公开(公告)日：2005-11-08
申请号：US10634413
申请日：2003-08-05
申请人： Somnath S. Nag , Girish A. Dixit , Srikanth Krishnan
发明人： Somnath S. Nag , Girish A. Dixit , Srikanth Krishnan
IPC分类号： H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/02131 , H01L21/022 , H01L21/02274 , H01L21/31612 , H01L21/31629 , H01L21/76801
摘要： A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).
摘要翻译：两阶段等离子体增强具有第一级低电容耦合RF偏压的电介质沉积，其具有适形沉积（202），随后是用于平坦化沉积的高电容耦合RF偏压（204），限制了在下面的结构上的电荷（104），106,108）。

9. 发明授权

US06287963B1 Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US06287963B1
公开(公告)日：2001-09-11
申请号：US08418257
申请日：1995-04-06
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L214763
CPC分类号： H01L23/53223 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/7684 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.
摘要翻译：提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。所有或一些沉积过程在允许沉积的铝原子的表面迁移的温度下以相对低的沉积速率发生。在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。沉积步骤被周期性地中断。

10. 发明授权

US5582971A Method of forming submicron contacts 失效
标题翻译：形成亚微米接触的方法
公开(公告)号：US5582971A
公开(公告)日：1996-12-10
申请号：US434371
申请日：1995-05-03
申请人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
发明人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/768
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成导体结构。在集成电路上形成介电层。在电介质层中形成接触开口，暴露下面的第一导电结构的一部分。在电介质层和接触开口中形成阻挡层。在阻挡层和接触开口中形成基本上共形的层。共形层被部分蚀刻掉，其中保形层仅保留在接触开口的底部。在阻挡层和剩余的保形层上形成第二导电层。

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