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1. 发明授权

US06905622B2 Electroless deposition method 有权
公开(公告)号：US06905622B2
公开(公告)日：2005-06-14
申请号：US10117712
申请日：2002-04-03
申请人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
发明人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
IPC分类号： C23C18/16 , H01L21/02 , H01L21/285 , H01L21/288 , H01L21/306 , H01L21/321 , H01L21/768 , B44C1/22 , B05D3/04 , B05D3/10
CPC分类号： H01L21/02074 , C23C18/1694 , C23C18/1831 , C23C18/1834 , C23C18/1851 , C23C18/1879 , C23C18/1882 , C23C18/1893 , C23C18/31 , C23C18/34 , C23C18/36 , C23C18/50 , H01L21/02068 , H01L21/28518 , H01L21/288 , H01L21/76843 , H01L21/76849 , H01L21/76874 , H01L2221/1089
摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.

2. 发明授权

US06899816B2 Electroless deposition method 有权
标题翻译：无电沉积法
公开(公告)号：US06899816B2
公开(公告)日：2005-05-31
申请号：US10117711
申请日：2002-04-03
申请人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
发明人： Deenesh Padhi , Joseph Yahalom , Sivakami Ramanathan , Chris R. McGuirk , Srinivas Gandikota , Girish Dixit
IPC分类号： C23C18/18 , H01L21/285 , H01L21/288 , H01L21/336 , H01L21/768 , B44C1/22 , B05D3/04 , B05D3/10
CPC分类号： H01L21/76843 , C23C18/1651 , C23C18/1893 , H01L21/28518 , H01L21/288 , H01L21/76849 , H01L21/76874 , H01L29/665 , H01L2221/1089
摘要： Methods and apparatus are provided for forming a metal or metal silicide layer by an electroless deposition technique. In one aspect, a method is provided for processing a substrate including depositing an initiation layer on a substrate surface, cleaning the substrate surface, and depositing a conductive material on the initiation layer by exposing the initiation layer to an electroless solution. The method may further comprise etching the substrate surface with an acidic solution and cleaning the substrate of the acidic solution prior to depositing the initiation layer. The initiation layer may be formed by exposing the substrate surface to a noble metal electroless solution or a borane-containing solution. The conductive material may be deposited with a borane-containing reducing agent. The conductive material may be used as a passivation layer, a barrier layer, a seed layer, or for use in forming a metal silicide layer.
摘要翻译：提供了通过无电沉积技术形成金属或金属硅化物层的方法和装置。在一个方面，提供了一种用于处理衬底的方法，包括在衬底表面上沉积起始层，清洁衬底表面，以及通过将引发层暴露于无电镀溶液而在引发层上沉积导电材料。该方法可以进一步包括用酸性溶液蚀刻衬底表面并在沉积起始层之前清洁酸性溶液的衬底。起始层可以通过将基材表面暴露于贵金属化学电解溶液或含硼烷溶液来形成。导电材料可以用含硼烷的还原剂沉积。导电材料可以用作钝化层，阻挡层，种子层，或用于形成金属硅化物层。

3. 发明授权

US06878245B2 Method and apparatus for reducing organic depletion during non-processing time periods 失效
标题翻译：在非处理时间段内减少有机物耗尽的方法和装置
公开(公告)号：US06878245B2
公开(公告)日：2005-04-12
申请号：US10085338
申请日：2002-02-27
申请人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Sivakami Ramanathan , Muhammad Atif Malik , Girish A. Dixit
发明人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Sivakami Ramanathan , Muhammad Atif Malik , Girish A. Dixit
IPC分类号： C25D21/14 , C25D21/18 , C25D17/00 , C25D21/00
CPC分类号： C25D21/18 , C25D21/14
摘要： Embodiments of the invention generally provide an apparatus and method for replenishing organic molecules in an electroplating bath. The replenishment process of the present invention may occur on a real-time basis, and therefore, the concentration of organics minimally varies from desired concentration levels. The replenishment method generally includes conducting pre-processing depletion measurements in order to determine organic depletion rates per current density applied in the electroplating system. Once the organic depletion rates per current density are determined, these depletion rates may be applied to an electroplating processing recipe to calculate the volume of organic depletion per recipe step. The calculated volume of organic depletion per recipe step may then be used to determine the volume of organic molecule replenishment per unit of time that is required per recipe step in order to maintain a desired concentration of organics in the plating solution. The calculated replenishment volume may then be added to the processing recipe so that the replenishment process may occur at real-time during processing periods. The apparatus generally includes a selectively actuated valve in communicaiton with a fluid delivery line, wherein the valve is configured to fluidly isolate a plating cell during a non-processing time period. The valve may be controlled by a system controller, and thus, the fluid level in the cell may be controlled during a non-processing time period.
摘要翻译：本发明的实施方案通常提供用于在电镀浴中补充有机分子的装置和方法。本发明的补充方法可以在实时的基础上进行，因此有机物的浓度最小化从期望的浓度水平变化。补充方法通常包括进行预处理耗尽测量，以便确定在电镀系统中施加的每个电流密度的有机耗尽率。一旦确定了每个电流密度的有机耗尽率，则这些耗尽率可以应用于电镀处理配方以计算每个配方步骤的有机耗尽量。然后可以使用每个配方步骤的计算的有机耗尽体积来确定每个配方步骤所需的每单位时间的有机分子补充体积，以维持电镀溶液中所需的有机物浓度。计算的补充量然后可以被添加到处理配方中，使得补货过程可以在处理时段期间实时发生。该装置通常包括与流体输送管线通信的选择性致动的阀，其中阀被配置为在非处理时间段期间流体地隔离电镀槽。阀可以由系统控制器控制，因此，可以在非处理时间段期间控制单元中的液位。

4. 发明授权

US06824666B2 Electroless deposition method over sub-micron apertures 有权
标题翻译：亚微米孔径上的无电沉积方法
公开(公告)号：US06824666B2
公开(公告)日：2004-11-30
申请号：US10059822
申请日：2002-01-28
申请人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Muhammad Atif Malik , Sivakami Ramanathan , Girish A. Dixit , Robin Cheung
发明人： Srinivas Gandikota , Chris R. McGuirk , Deenesh Padhi , Muhammad Atif Malik , Sivakami Ramanathan , Girish A. Dixit , Robin Cheung
IPC分类号： C23C2800
CPC分类号： H01L21/76843 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1831 , C23C18/28 , C23C18/30 , C23C18/38 , H01L21/288 , H01L21/2885 , H01L21/6708 , H01L21/76864 , H01L21/76868 , H01L21/76871 , H01L21/76874 , H01L21/76877 , H01L2221/1089 , Y10S428/936
摘要： An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.
摘要翻译：一种沉积包含至少一种选自贵金属，半贵金属，其合金及其组合的金属的催化剂层的装置和方法，其形成在基板上形成的亚微米特征。贵金属的实例包括钯和铂。半贵金属的实例包括钴，镍和钨。可通过无电沉积，电镀或化学气相沉积来沉积催化层。在一个实施方案中，催化层可以沉积在特征中以用作随后沉积的导电材料的阻挡层。在另一个实施方案中，催化剂层可以沉积在阻挡层上。在另一个实施方案中，催化层可以沉积在沉积在阻挡层上的种子层上，以充当种子层中任何不连续性的“贴片”。一旦沉积了催化层，可以在催化剂层上沉积诸如铜的导电材料。在一个实施例中，导电材料通过无电沉积沉积在催化剂层上。在另一个实施方案中，导电材料通过无电沉积然后电镀或随后进行化学气相沉积沉积在催化剂层上。在另一个实施例中，导电材料通过电镀或化学气相沉积沉积在催化层上。

5. 发明申请

US20050136185A1 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application 审中-公开
标题翻译：后冲洗以改善无电钴在铜上的选择性沉积，用于ULSI应用
公开(公告)号：US20050136185A1
公开(公告)日：2005-06-23
申请号：US10979078
申请日：2004-10-29
申请人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish Dixit
发明人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish Dixit
IPC分类号： B05D1/40 , B05D3/00 , C23C18/16 , C23C18/31 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/302 , H01L21/31 , H01L21/44 , H01L21/461 , H01L21/768
CPC分类号： H01L21/76877 , C23C18/166 , C23C18/1831 , C23C18/1834 , C23C18/1879 , C23C18/1882 , C23C18/34 , C23C18/36 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/76814 , H01L21/76849 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76883
摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.
摘要翻译：提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用酸性溶液。在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。

6. 发明授权

US06821909B2 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application 失效
标题翻译：后冲洗以改善无电钴在铜上的选择性沉积，用于ULSI应用
公开(公告)号：US06821909B2
公开(公告)日：2004-11-23
申请号：US10284855
申请日：2002-10-30
申请人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
发明人： Sivakami Ramanathan , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
IPC分类号： H01L2131
CPC分类号： H01L21/76877 , C23C18/166 , C23C18/1831 , C23C18/1834 , C23C18/1879 , C23C18/1882 , C23C18/34 , C23C18/36 , C23C18/44 , C23C18/50 , C23G1/10 , H01L21/288 , H01L21/76814 , H01L21/76849 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76883
摘要： A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.
摘要翻译：提供了使用一种或多种电镀技术在衬底表面上沉积钝化层的方法。该方法的实施例包括通过将衬底表面暴露于第一无电解溶液来选择性地沉积引发层，通过将引发层暴露于第二无电解溶液来沉积起始层上的钝化材料，并用酸性溶液。在另一方面，该方法包括在施加酸性溶液期间将超声波或兆声波能量施加到基底表面。在另一方面，该方法包括使用酸性溶液去除大约至大约200埃的钝化材料。在另一方面，该方法包括在沉积起始层之前用第一酸性溶液清洗基底表面。

7. 发明授权

US06951599B2 Electropolishing of metallic interconnects 失效
标题翻译：电抛光金属互连
公开(公告)号：US06951599B2
公开(公告)日：2005-10-04
申请号：US10188163
申请日：2002-07-01
申请人： Joseph Yahalom , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
发明人： Joseph Yahalom , Deenesh Padhi , Srinivas Gandikota , Girish A. Dixit
IPC分类号： C25F3/16 , C25F3/22 , C25F7/00
CPC分类号： C25F3/16 , C25F3/22
摘要： Embodiments of the present invention generally relate to a method and apparatus for planarizing a substrate by electropolishing techniques. Certain embodiments of an electropolishing apparatus include a contact ring adapted to support a substrate, a cell body adapted to hold an electropolishing solution, a fluid supply system adapted to provide the electropolishing solution to the cell body, a cathode disposed within the cell body, a power supply system in electrical communication with the contact ring and the cathode, and a controller coupled to at least the fluid supply system and the power supply system. The controller may be adapted to provide a first set of electropolishing conditions to form a boundary layer between the substrate and the electropolishing solution to an initial thickness and may be adapted to provide a second set of electropolishing conditions to control the boundary layer to a subsequent thickness less than or equal to the initial thickness.
摘要翻译：本发明的实施例一般涉及通过电抛光技术来平坦化衬底的方法和装置。电抛光装置的某些实施例包括适于支撑基底的接触环，适于保持电解抛光溶液的电池体，适于将电解抛光溶液提供给电池体的流体供应系统，设置在电池体内的阴极，电源系统与接触环和阴极电连通，以及控制器，耦合到至少流体供应系统和电源系统。控制器可以适于提供第一组电抛光条件，以在衬底和电解抛光溶液之间形成初始厚度的边界层，并且可适于提供第二组电抛光条件以将边界层控制到随后的厚度小于或等于初始厚度。

8. 发明授权

US06723224B2 Electro-chemical polishing apparatus 有权
标题翻译：电化学抛光装置
公开(公告)号：US06723224B2
公开(公告)日：2004-04-20
申请号：US09920704
申请日：2001-08-01
申请人： Joseph Yahalom , Srinivas Gandikota , Christopher R. McGuirk , Deenesh Padhi
发明人： Joseph Yahalom , Srinivas Gandikota , Christopher R. McGuirk , Deenesh Padhi
IPC分类号： B23H300
CPC分类号： C25F7/00 , H01L21/6708
摘要： Generally, a method and apparatus for electro-chemical polishing a metal layer disposed on a substrate is provided. In one embodiment, the electro-chemical polishing apparatus generally includes a substrate support having a plurality of contact members, a cathode and at least one nozzle. The nozzle is adapted to centrally dispose a polishing fluid on the substrate supported by the substrate support. The cathode is adapted to couple the polishing fluid to a negative terminal of a power source. A positive terminal of the power source is electrically coupled through the contact members to the conductive layer of the substrate. The nozzle creates a turbulent flow in the portion of the polishing fluid boundary layer proximate the center of the substrate which enhances the polishing rate at the center of the substrate.
摘要翻译：通常，提供了一种用于电化学抛光设置在基底上的金属层的方法和装置。在一个实施例中，电化学抛光装置通常包括具有多个接触构件，阴极和至少一个喷嘴的衬底支撑件。喷嘴适于将抛光流体集中设置在由基板支撑件支撑的基板上。阴极适于将抛光流体耦合到电源的负极端子。电源的正端子通过接触构件电耦合到衬底的导电层。喷嘴在抛光液边界层的靠近基板中心的部分产生湍流，这增强了基板中心处的抛光速率。

9. 发明授权

US07205228B2 Selective metal encapsulation schemes 失效
标题翻译：选择性金属封装方案
公开(公告)号：US07205228B2
公开(公告)日：2007-04-17
申请号：US10812480
申请日：2004-03-30
申请人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
发明人： Deenesh Padhi , Srinivas Gandikota , Mehul Naik , Suketu A. Parikh , Girish A. Dixit
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/288 , H01L21/76829 , H01L21/7685 , H01L21/76885
摘要： A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.
摘要翻译：在一个或多个实施例中，处理半导体衬底的方法和系统包括在衬底表面上沉积保护层，所述保护层包括布置在电介质材料中的导电元件; 处理所述保护层以暴露所述导电元件; 将金属钝化层无电沉积到导电元件上; 以及在无电沉积之后从衬底去除保护层的至少一部分。在另一方面，一种处理半导体的方法和系统包括在包括导电元件的衬底表面上沉积金属钝化层，掩蔽钝化层以保护衬底表面的下面的导电元件，去除未屏蔽的钝化层，以及去除掩模从钝化层。

10. 发明申请

US20070082479A1 Chemical mechanical polishing techniques for integrated circuit fabrication 审中-公开
标题翻译：用于集成电路制造的化学机械抛光技术
公开(公告)号：US20070082479A1
公开(公告)日：2007-04-12
申请号：US11245677
申请日：2005-10-06
申请人： Deenesh Padhi , Girish Dixit
发明人： Deenesh Padhi , Girish Dixit
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76819 , H01L21/7684 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a planarized top surface. The dielectric layer is not planarized at this stage of the process. A pre-planarizing thickness profile of the non-planarized dielectric layer is determined and recorded. An interconnect line trench is then etched through the dielectric layer. A sandwich layer including a conductive Cu diffusion barrier layer and a Cu seed layer is deposited in the trench and on the dielectric layer. A Cu comprising metal is deposited in the sandwich lined trench. A Cu metal overburden is thereby deposited on the section of the sandwich layer that is positioned on the dielectric layer. A first CMP process is used to remove the Cu overburden and the Cu seed layer that is formed in the sandwich layer portion on the dielectric layer. A second CMP process is utilized wherein the pre-planarizing thickness profile is employed to remove the Cu barrier layer from the top surface of the dielectric layer, the second CMP process is then continued by planarizing the dielectric layer to form a substantially uniform flat surface having a substantially uniform thickness which is substantially equal to a predetermined design thickness. The second CMP process thereby results in fabricating a dielectric layer wherein substantially all interconnect lines have a substantially uniform thickness that is substantially equal to the design thickness for the dielectric layer.
摘要翻译：本发明提供用于制造用于半导体晶片制造的水平互连线的方法。介电层沉积在具有平坦化顶表面的电介质叠层上。在该过程的这个阶段，电介质层不被平坦化。确定并记录非平面化电介质层的预平面化厚度分布。然后通过介电层蚀刻互连线沟槽。包含导电性Cu扩散阻挡层和Cu籽晶层的夹层被沉积在沟槽和电介质层上。包含金属的Cu沉积在夹层衬里的沟槽中。因此，在位于电介质层上的夹层的部分上沉积Cu金属覆盖层。使用第一CMP工艺来去除在电介质层上的夹层结构部分中形成的Cu覆盖层和Cu籽晶层。使用第二CMP工艺，其中使用预平面化厚度轮廓来从电介质层的顶表面去除Cu阻挡层，然后通过平坦化介电层来继续进行第二CMP工艺以形成基本上均匀的平坦表面，其具有基本均匀的厚度，其基本上等于预定的设计厚度。因此，第二CMP工艺导致制造介电层，其中基本上所有的互连线具有基本上等于介电层的设计厚度的基本均匀的厚度。

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