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    • 6. 发明授权
    • Optical integrated circuits (ICs)
    • 光集成电路(IC)
    • US07087179B2
    • 2006-08-08
    • US09734950
    • 2000-12-11
    • Cecilia Y. MakJohn M. WhiteKam S. LawDan Maydan
    • Cecilia Y. MakJohn M. WhiteKam S. LawDan Maydan
    • B29D11/00
    • G02B6/12004G02B6/13G02B6/132
    • In one aspect, the invention provides methods and apparatus for forming optical devices on large area substrates. The large area substrates are preferably made of quartz, silica or fused silica. The large area substrates enable larger optical devices to be formed on a single die. In another aspect, the invention provides methods and apparatus for forming integrated optical devices on large area substrates, such as quartz, silica or fused silica substrates. In another aspect, the invention provides methods and apparatus for forming optical devices using damascene techniques on large area substrates or silicon substrates. In another aspect, methods for forming optical devices by bonding an upper cladding layer on a lower cladding and a core is provided.
    • 一方面,本发明提供了用于在大面积基板上形成光学装置的方法和装置。 大面积基板优选由石英,二氧化硅或熔融二氧化硅制成。 大面积基板使得能够在单个管芯上形成更大的光学器件。 另一方面,本发明提供了用于在大面积衬底(例如石英,二氧化硅或熔融二氧化硅衬底)上形成集成光学器件的方法和装置。 在另一方面,本发明提供了使用大面积衬底或硅衬底上的镶嵌技术形成光学器件的方法和装置。 在另一方面,提供了通过将下包层和芯上的上包层结合来形成光器件的方法。
    • 8. 再颁专利
    • Process for PECVD of silicon oxide using TEOS decomposition
    • USRE36623E
    • 2000-03-21
    • US752972
    • 1996-12-02
    • David Nin-Kou WangJohn M. WhiteKam S. LawCissy LeungSalvador P. UmotoyKenneth S. CollinsJohn A. AdamikIlya PerlovDan Maydan
    • David Nin-Kou WangJohn M. WhiteKam S. LawCissy LeungSalvador P. UmotoyKenneth S. CollinsJohn A. AdamikIlya PerlovDan Maydan
    • C23C16/40C23C16/44C23C16/455C23C16/509C23C16/54H01L21/314H01L21/316H05H1/24
    • C23C16/45565C23C16/402C23C16/455C23C16/45521C23C16/5096C23C16/54H01J37/32082H01J37/3244H01L21/31604
    • A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.