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    • 4. 发明授权
    • n-bit analog-to-digital converter with n-1 magnitude amplifiers and n
comparators
    • 具有n-1幅度放大器和n个比较器的n位模数转换器
    • US5684419A
    • 1997-11-04
    • US347909
    • 1994-12-01
    • Frank MurdenCarl W. Moreland
    • Frank MurdenCarl W. Moreland
    • H03F3/26H03F3/45H03M1/44H03M1/12H03M1/46
    • H03F3/26H03F3/45103H03F3/45107H03M1/445H03F2203/45302H03F2203/45311H03F2203/45318H03F2203/45352H03F2203/45371H03F2203/45702H03F2203/45722
    • A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V.sub.OL and V.sub.OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V.sub.A, on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.
    • 串行型A / D转换器使用幅度放大器(“magamps”)和比较器来实现将模拟信号转换为灰度代码信号,然后将其转换为二进制数字信号,通过灰度代码对二进制部分 串行型A / D转换器。 更具体地,串行型A / D转换器使用具有n-1个magamp和n比较器的n位转换器。 级联的n-1型卡子使得一级的VOL和VOH输出是下一级的输入。 比较器的输出被输入到串行A / D转换器的灰度代码到二进制部分。 比较器的锁存发生在卡盘之外。 这允许n个比较器的并联闭锁。 串行型A / D转换器的速度由卡盘的带宽决定。 串行型A / D转换器包括一种偏移方法,可显着降低早期电压VA对输出波形的影响。 串行型A / D转换器的每个级可以具有任何期望的增益,而不限于特定的增益。
    • 5. 发明授权
    • Integrated-circuit structures and methods for correction of temperature and process-induced parameter errors
    • 用于校正温度和工艺引起的参数误差的集成电路结构和方法
    • US06246353B1
    • 2001-06-12
    • US09394632
    • 1999-09-13
    • Michael R. ElliottFrank Murden
    • Michael R. ElliottFrank Murden
    • H03M112
    • H03M1/089H03F1/302H03M1/167
    • Integrated-circuit structures and methods are provided for generating an error signal that represents temperature and process-induced signal changes in transistor parameters. In particular, a reference transistor and a sense transistor are biased to each generate a substantially temperature-insensitive minority-carrier current. The reference transistor is provided with a substantially constant voltage across its current terminals to convert its minority-carrier current into a substantially temperature-insensitive reference current IR. In contrast, the sense transistor is provided with a temperature-varying voltage across its current terminals to convert its minority-carrier current into a temperature-varying sense current IS. The reference current and the sense current are then differenced to realize an error signal IE that contains information that describes temperature and process-induced signal errors in integrated-circuit transistor stages. The error signal is especially useful for correcting signal errors in circuits that cannot accommodate conventional signal-stabilizing circuitry because that circuitry would degrade circuit operation.
    • 提供了集成电路结构和方法,用于产生表示晶体管参数中的温度和过程感应信号变化的误差信号。 特别地,参考晶体管和感测晶体管被偏置以产生基本上不受温度影响的少数载流子电流。 参考晶体管在其电流端子上设置有基本上恒定的电压,以将其少数载流子电流转换成基本上不受温度影响的参考电流IR。 相比之下,感测晶体管在其电流端子上设置有温度变化的电压,以将其少数载流子电流转换成温度变化的感测电流IS。 然后,参考电流和感测电流被差分化以实现包含描述集成电路晶体管级中的温度和处理引起的信号误差的信息的误差信号IE。 误差信号对于校正不能适应常规信号稳定电路的电路中的信号误差特别有用,因为该电路将降低电路操作。
    • 7. 发明授权
    • Control systems and methods for reducing residue signal offset in subranging analog-to-digital converters
    • 减少模数转换器中的残留信号偏移的控制系统和方法
    • US06323791B1
    • 2001-11-27
    • US09416982
    • 1999-10-13
    • Frank MurdenJoe Young
    • Frank MurdenJoe Young
    • H03M100
    • H03M1/0607H03M1/167
    • Feedback control systems and methods are provided for correcting residue signal offset errors in subranging ADCs. The systems and methods eliminate clock-to-clock offset changes and reduce noise generation. An exemplary control system includes a feedback loop around a residue sampler and a residue amplifier that includes a) a feedback sampler that resamples the output signal of the residue sampler to produce a resampled residue signal, and b) an offset current generator that delivers an offset current to the residue amplifier with a current magnitude that is responsive to the resampled residue signal. The sampling of the residue and feedback samplers is time shifted to block the propagation of spurious signals that are typically generated in DACs of the subranging structure.
    • 提供反馈控制系统和方法来校正子载波ADC中的残留信号偏移误差。 系统和方法消除了时钟到时钟的偏移变化并减少了噪声的产生。 示例性控制系统包括残留采样器周围的反馈回路和残余放大器,其包括:a)反馈采样器,其重新采样残留采样器的输出信号以产生再采样的残留信号,以及b)偏移电流发生器,其输出偏移 电流到残余放大器,其具有响应于再采样残留信号的电流幅度。 残留物和反馈采样器的采样被时移,以阻止通常在子结构的DAC中产生的寄生信号的传播。
    • 8. 发明授权
    • Analog to digital converter using complementary differential emitter
pairs
    • 使用互补差分发射极对的模数转换器
    • US5550492A
    • 1996-08-27
    • US347910
    • 1994-12-01
    • Frank Murden
    • Frank Murden
    • H03M1/34H03F3/26H03F3/45H03M1/44H03K5/24H03M1/72
    • H03F3/45596H03F3/26H03F3/45085H03M1/445H03F2203/45612
    • A differential amplifier operating as a magnitude amplifier may be used in a serial-type A/D converter. The differential amplifier uses complementary differential emitter pairs for folding and aligning a differential input signal. The differential input signal has a first signal and a second signal each of which is fed to one of two input circuits. One input circuit includes a bipolar npn transistor and a current sink and the other includes a bipolar pnp transistor and a current source. The outputs of the input npn transistors feed a differential pair of output pnp transistors. The emitters of the output pnp transistors are coupled, with the signal on the emitters following the lower of the differential input signals. The outputs of the input pnp transistors feed a differential pair of output npn transistors. The emitters of the output npn transistors also are coupled, with the signal on the emitters following the inputs in a predetermined manner. The results are folded signals at the outputs of the output transistors that are aligned by offset circuits.
    • 作为幅度放大器工作的差分放大器可用于串行型A / D转换器。 差分放大器使用互补差分发射器对来折叠和对准差分输入信号。 差分输入信号具有第一信号和第二信号,每个信号被馈送到两个输入电路之一。 一个输入电路包括双极性npn晶体管和电流吸收器,另一个包括双极pnp晶体管和电流源。 输入npn晶体管的输出馈送输出pnp晶体管的差分对。 输出pnp晶体管的发射极被耦合,发射极上的信号跟随差分输入信号的较低者。 输入pnp晶体管的输出馈送差分输出npn晶体管对。 输出npn晶体管的发射极也被耦合,发射器上的信号以预定的方式跟随输入。 结果是在由偏移电路对准的输出晶体管的输出处的折叠信号。