专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06686864B1 Pipelined analog-to-digital converters with gain-matching structures 有权
标题翻译：具有增益匹配结构的流水线模数转换器
公开(公告)号：US06686864B1
公开(公告)日：2004-02-03
申请号：US10229039
申请日：2002-08-28
申请人： Carl W. Moreland
发明人： Carl W. Moreland
IPC分类号： H03M138
CPC分类号： H03M1/0604 , H03M1/167
摘要： Pipelined ADC systems are provided with gain-matching structures that substantially eliminate gain errors between preceding and succeeding converter stages. These structures include reference signal-conditioning elements which mimic at least one of main signal-conditioning elements in the succeeding converter stages. The reference signal-conditioning elements control reference signals which maintain a match between the full-scale range of a digital-to-analog converter (DAC) in a succeeding stage and the “gained-up” step size of a DAC in a preceding stage. This match substantially eliminates the gain errors.
摘要翻译：流水线ADC系统提供增益匹配结构，基本上消除了前一个和后一个转换器级之间的增益误差。这些结构包括模拟后续转换器级中的主信号调节元件中的至少一个的参考信号调节元件。参考信号调理元件控制参考信号，其保持后级中的数模转换器（DAC）的满量程范围与前一级中的DAC的“增大”步长之间的匹配。该匹配基本上消除了增益误差。

2. 发明授权

US06307491B1 Trim systems and methods having temporary and permanent operational modes 有权
标题翻译：修剪系统和方法具有临时和永久的操作模式
公开(公告)号：US06307491B1
公开(公告)日：2001-10-23
申请号：US09512730
申请日：2000-02-24
申请人： Carl W. Moreland , Russel G. Stop
发明人： Carl W. Moreland , Russel G. Stop
IPC分类号： H03M110
CPC分类号： H03M1/1061 , H03M1/46 , H03M1/745 , H03M1/785
摘要： Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.
摘要翻译：锁存系统和方法被配置为在设定和复位状态的实验组合中临时锁存微调信号，并且随后以优选组合（即，优化电子电路的性能参数的组合）永久地锁存微调信号。本发明的闩锁系统包括闩锁，复位驱动器，临时设置驱动器和永久设置驱动器，并且特别适用于在永久锁定该优选组合之前确定设置和复位状态的优选组合。

3. 发明授权

US06294902B1 Bandgap reference having power supply ripple rejection 有权
标题翻译：具有电源纹波抑制的带隙基准
公开(公告)号：US06294902B1
公开(公告)日：2001-09-25
申请号：US09637807
申请日：2000-08-11
申请人： Carl W. Moreland , Marvin J. Young
发明人： Carl W. Moreland , Marvin J. Young
IPC分类号： G05F140
CPC分类号： G05F3/30
摘要： A bandgap reference circuit provides an output reference voltage that is generally insensitive to fluctuations in supply voltage, ambient temperature, and output load current. A current regulator establishes an output whose variations are reduced, preferably logarithmically, relative to variations in a supply voltage. A bandgap generator fed by the output current provides an output reference voltage with similarly suppressed variations. A control amplifier biases the bandgap generator to provide a high level common-mode rejection of various error sources.
摘要翻译：带隙参考电路提供对电源电压，环境温度和输出负载电流波动通常不敏感的输出参考电压。电流调节器建立相对于电源电压变化优选对数减小的输出。由输出电流馈送的带隙发生器提供具有类似抑制变化的输出参考电压。控制放大器偏置带隙发生器以提供各种误差源的高电平共模抑制。

4. 发明授权

US5534794A Selectable logic output stage 失效
标题翻译：可选逻辑输出级
公开(公告)号：US5534794A
公开(公告)日：1996-07-09
申请号：US347710
申请日：1994-12-01
申请人： Carl W. Moreland
发明人： Carl W. Moreland
IPC分类号： H03K19/0175
CPC分类号： H03K19/017581
摘要： A logic output stage that may be part of a circuit that provides the circuit user with the ability to select the type of digital electronic format for the digital signals output from the circuit. The logic output stage may include separate sections for processing signals so that they will have one of a plurality of digital electronic formats. Moreover, in cases where two or more digital electronic formats are very close, a single section may be used to process digital signals to have these formats.
摘要翻译：逻辑输出级可以是电路的一部分，为电路用户提供从电路输出的数字信号选择数字电子格式的类型的能力。逻辑输出级可以包括用于处理信号的单独部分，使得它们将具有多个数字电子格式之一。此外，在两个或多个数字电子格式非常接近的情况下，可以使用单个部分来处理数字信号以具有这些格式。

5. 发明授权

US06753732B1 Accurate, wide-band, low-noise variable-gain amplifier structures and gain control methods 有权
标题翻译：精确，宽带，低噪声可变增益放大器结构和增益控制方法
公开(公告)号：US06753732B1
公开(公告)日：2004-06-22
申请号：US10364163
申请日：2003-02-10
申请人： Carl W. Moreland
发明人： Carl W. Moreland
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F3/45089 , H03F3/45506 , H03F3/45511 , H03F2203/45362 , H03F2203/45508 , H03F2203/45642 , H03F2203/45651 , H03F2203/45694 , H03F2203/45722 , H03G1/0023 , H03G3/001
摘要： Variable-gain amplifiers (VGAs) are provided that realize gain accuracy (e.g., over variations in temperature and fabrication processes) while also providing this accuracy over a wide bandwidth and without the signal-to-noise degradation typically associated with signal attentuating elements. Differential signal and gain amplifiers of these VGAs include current sources which are controlled by a common error signal Serr. The gain amplifier is supplemented by feedback structure that generates the error signal Serr and controls the amplifier's transconductance to be the ratio of at least one of currents and resistors. Because such ratios can be well matched (especially in integrated circuit realizations of the variable-gain amplifiers) and because the current source of the signal amplifier is also controlled by the error signal Serr, this wide-band, low-noise open-loop amplifier's gain is accurately controlled.
摘要翻译：提供了可变增益放大器（VGA），其实现增益精度（例如，在温度和制造工艺上的变化），同时还可以在宽带宽上提供该精度，而不会通常与信号注意元件相关联的信噪比降低。这些VGA的差分信号和增益放大器包括由公共误差信号Serr控制的电流源。增益放大器由产生误差信号Serr的反馈结构补充，并将放大器的跨导控制为电流和电阻中至少一个的比例。因为这样的比率可以很好地匹配（特别是在可变增益放大器的集成电路实现中），并且由于信号放大器的电流源也由误差信号Serr控制，所以该宽带低噪声开环放大器增益准确控制。

6. 发明授权

US08749240B1 Time domain method and apparatus for metal detectors 有权
标题翻译：金属探测器的时域方法和装置
公开(公告)号：US08749240B1
公开(公告)日：2014-06-10
申请号：US13235950
申请日：2011-09-19
申请人： Eric Foster , John L. Earle , Carl W. Moreland
发明人： Eric Foster , John L. Earle , Carl W. Moreland
IPC分类号： G01V3/10
CPC分类号： G01V3/10
摘要： This invention provides a pulse induction metal detector where a coil transmits a pulsed magnetic field to energize metal objects that are often buried or hidden in a matrix (ground) containing ferromagnetic minerals. A difficult challenge is to detect and identify the metal object while ignoring the ferromagnetic matrix. Techniques are presented for achieving this.
摘要翻译：本发明提供了一种脉冲感应金属检测器，其中线圈传送脉冲磁场以激励通常被掩埋或隐藏在包含铁磁性矿物的基体（地面）中的金属物体。一个困难的挑战是在忽略铁磁矩阵的同时检测和识别金属物体。提出了实现这一点的技术。

7. 发明授权

US06822519B1 Synthesizer structures and alignment methods that facilitate quadrature demodulation 有权
标题翻译：合成器结构和对准方法，促进正交解调
公开(公告)号：US06822519B1
公开(公告)日：2004-11-23
申请号：US10364162
申请日：2003-02-10
申请人： Carl W. Moreland , Bryan S. Puckett
发明人： Carl W. Moreland , Bryan S. Puckett
IPC分类号： H03L700
CPC分类号： H03J1/005 , H03D7/165 , H03J2200/03 , H03L7/099 , H03L7/18 , H03L7/199
摘要： Synthesizer structures and alignment methods are provided that facilitate quadrature demodulation. The structures are realized with phase-locked loops that include half-rate frequency dividers to provide loop output signals with a wide range of output frequencies and with frequency dividers that provide quadrature signals in response to the output signals. The structures include controllers that direct alignment methods which lock a VCO to a reference signal from a reference frequency divider to thereby provide the output signals.
摘要翻译：提供了促进正交解调的合成器结构和对准方法。这些结构通过包括半速率分频器的锁相环实现，以提供具有宽范围输出频率的环路输出信号，以及响应于输出信号提供正交信号的分频器。这些结构包括控制器，其将对准方法引导到将参考信号从参考分频器锁定，从而提供输出信号。

8. 发明授权

US06304201B1 Precision digital-to-analog converters and methods having programmable trim adjustments 有权
标题翻译：精密数模转换器和方法具有可编程的修整调整
公开(公告)号：US06304201B1
公开(公告)日：2001-10-16
申请号：US09489955
申请日：2000-01-24
申请人： Carl W. Moreland , Russel G. Stop
发明人： Carl W. Moreland , Russel G. Stop
IPC分类号： H03M110
CPC分类号： H03M1/1061 , H03M1/745 , H03M1/785
摘要： N-bit precision digital-to-analog converters are provided that facilitate realization of precision linearities (i.e., linearities that substantially exceed N-bit linearity). They include a binary-weighted current source, current switches and bidirectional-trim digital-to-analog converters. The binary-weighted current source generates binary-weighted currents that are each coupled to the output port by a respective one of the current switches in response to a respective bit of the digital input signal. The bidirectional-trim digital-to-analog converters generate respective bidirectional trim currents with respective amplitudes and directions. Each of the bidirectional-trim digital-to-analog converters is coupled to provide its bidirectional trim current to a respective one of the current switches for a linearizing adjustment of that switch's binary-weighted current. Preferably, the bidirectional-trim currents are slaved to the binary-weighted currents.
摘要翻译：提供了有助于实现精确线性度（即，大大超过N位线性度的线性度）的N位精度数模转换器。它们包括二进制加权电流源，电流开关和双向微调数模转换器。二进制加权电流源产生二进制加权电流，其响应于数字输入信号的相应位而由相应的一个电流开关耦合到输出端口。双向微调数模转换器产生各自的幅度和方向的双向微调电流。每个双向微调数模转换器被耦合以向其中的相应一个电流开关提供其双向微调电流，以便对该开关的二进制加权电流进行线性化调整。优选地，双向调整电流被从属于二进制加权电流。

9. 发明授权

US06191619B1 Translators and methods for converting differential signals to single-ended signals 有权
标题翻译：用于将差分信号转换为单端信号的转换器和方法
公开(公告)号：US06191619B1
公开(公告)日：2001-02-20
申请号：US09382046
申请日：1999-08-24
申请人： Carl W. Moreland , Michael R. Elliott
发明人： Carl W. Moreland , Michael R. Elliott
IPC分类号： H03K19086
CPC分类号： H03K19/01812
摘要： High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced. Translator speed is further enhanced with elements associated with the current-diverting transistors that prevent saturation in the current mirrors and the complimentary output stage.
摘要翻译：提供高速信号转换器以将差分输入信号（例如，ECL信号）转换为单端输出信号（例如，CMOS信号）。示例性的翻译器由第一和第二电流镜，第一和第二互补差分晶体管对，互补晶体管输出级以及第一和第二电流转向晶体管形成。辅助输出级最初产生单端输出信号，以响应从互补差分对接收的电流。当输出信号已经建立时，电流 - 转向晶体管通过承载由互补差分对提供的电流的至少一部分来进行响应。电流转向晶体管还驱动电流镜以将这些电流的其它部分转移到互补输出级。相应地减少输出级中的存储电荷并提高其响应时间。转换器速度进一步增强与电流转移晶体管相关联的元件，其防止电流镜和补偿输出级中的饱和。

10. 发明授权

US5684419A n-bit analog-to-digital converter with n-1 magnitude amplifiers and n comparators 失效
标题翻译：具有n-1幅度放大器和n个比较器的n位模数转换器
公开(公告)号：US5684419A
公开(公告)日：1997-11-04
申请号：US347909
申请日：1994-12-01
申请人： Frank Murden , Carl W. Moreland
发明人： Frank Murden , Carl W. Moreland
IPC分类号： H03F3/26 , H03F3/45 , H03M1/44 , H03M1/12 , H03M1/46
CPC分类号： H03F3/26 , H03F3/45103 , H03F3/45107 , H03M1/445 , H03F2203/45302 , H03F2203/45311 , H03F2203/45318 , H03F2203/45352 , H03F2203/45371 , H03F2203/45702 , H03F2203/45722
摘要： A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V.sub.OL and V.sub.OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V.sub.A, on the output waveforms. Each stage of the serial-type A/D converter may have any desired gain and not limited to a particular gain.
摘要翻译：串行型A / D转换器使用幅度放大器（“magamps”）和比较器来实现将模拟信号转换为灰度代码信号，然后将其转换为二进制数字信号，通过灰度代码对二进制部分串行型A / D转换器。更具体地，串行型A / D转换器使用具有n-1个magamp和n比较器的n位转换器。级联的n-1型卡子使得一级的VOL和VOH输出是下一级的输入。比较器的输出被输入到串行A / D转换器的灰度代码到二进制部分。比较器的锁存发生在卡盘之外。这允许n个比较器的并联闭锁。串行型A / D转换器的速度由卡盘的带宽决定。串行型A / D转换器包括一种偏移方法，可显着降低早期电压VA对输出波形的影响。串行型A / D转换器的每个级可以具有任何期望的增益，而不限于特定的增益。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式