专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07685411B2 Multi-mode instruction memory unit 有权
标题翻译：多模式指令存储单元
公开(公告)号：US07685411B2
公开(公告)日：2010-03-23
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译：指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从如果目标指令没有存储在第二存储器结构中的第一存储器结构。

2. 发明授权

US08990543B2 System and method for generating and using predicates within a single instruction packet 有权
标题翻译：用于在单个指令包内生成和使用谓词的系统和方法
公开(公告)号：US08990543B2
公开(公告)日：2015-03-24
申请号：US12045825
申请日：2008-03-11
申请人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
发明人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
IPC分类号： G06F15/80 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译：在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行管道。该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。

3. 发明申请

US20090235051A1 System and Method of Selectively Committing a Result of an Executed Instruction 有权
标题翻译：选择性地执行执行指令的结果的系统和方法
公开(公告)号：US20090235051A1
公开(公告)日：2009-09-17
申请号：US12045825
申请日：2008-03-11
申请人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
发明人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译：在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行管道。该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。

4. 发明授权

US5949436A Accelerated graphics port multiple entry gart cache allocation system and method 失效
标题翻译：加速图形端口多进入gart缓存分配系统和方法
公开(公告)号：US5949436A
公开(公告)日：1999-09-07
申请号：US941861
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
IPC分类号： G06F12/10 , G06T1/60 , G06F15/00 , G06T1/00
CPC分类号： G06T1/60 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组使用，将AGP图形控制器使用的虚拟内存地址重新映射到驻留在计算机系统内存中的物理内存地址GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际使用不连续的块或物理系统存储器的页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针。核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。当缓存中没有找到GART表条目时，需要内存访问才能获取所需的GART表条目。在内存读取访问返回的内存信息的缓存行的切换模式下，每个四字中有两个GART表条目。由于缓存未命中，每次需要存储器访问时，至少有一个四字（两个GART表条目）存储在缓存中。

5. 发明授权

US06470429B1 System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops 有权
标题翻译：用于将内存请求识别为非缓存或减少缓存一致性目录查找和总线侦听的系统
公开(公告)号：US06470429B1
公开(公告)日：2002-10-22
申请号：US09752128
申请日：2000-12-29
申请人： Phillip M. Jones , Robert Allan Lester
发明人： Phillip M. Jones , Robert Allan Lester
IPC分类号： G06F1200
CPC分类号： G06F12/0835 , G06F12/0831 , G06F12/0888
摘要： An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.
摘要翻译：用于在具有多个处理器的计算机系统中将对主存储器的请求识别为不可缓存的装置包括全部耦合到主桥单元（北桥）的主存储器，存储器高速缓存，处理器和高速缓存一致性目录。处理器通过主机桥单元向主存储器发送数据请求。主机桥单元包括高速缓存一致性控制器，其执行协议以维持存储在计算机系统中的每个处理器高速缓存中的数据的一致性。高速缓存一致性目录连接到高速缓存一致性控制器。在从主存储器接收到数据请求之后，主桥单元将对主存储器的数据请求标识为可高速缓存或不可缓存。如果数据不可缓存，则主机桥单元不请求高速缓存一致性控制器执行高速缓存一致性目录查找以维持数据的一致性。

6. 发明授权

US5990914A Generating an error signal when accessing an invalid memory page 失效
标题翻译：访问无效内存页面时产生错误信号
公开(公告)号：US5990914A
公开(公告)日：1999-11-23
申请号：US926425
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F11/07 , G06F13/16
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0745 , G06F3/14
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。其中一个功能标志用作相应存储器页面的当前位。当特征标志当前位被设置时，存储器页面已被保留在用于图形数据的物理存储器中，并且可以执行地址转换。当特征标志当前位清除时，存储器页面尚未被保留用于物理存储器中的图形数据，然后必须确定是否执行转换或者向计算机处理器生成错误信号。

7. 发明授权

US5936640A Accelerated graphics port memory mapped status and control registers 失效
标题翻译：加速图形端口存储器映射状态和控制寄存器
公开(公告)号：US5936640A
公开(公告)日：1999-08-10
申请号：US941862
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F12/10 , G06F15/00 , G06F12/06
CPC分类号： G06F3/14 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。多个AGP存储器映射状态和控制寄存器存储在计算机系统存储器中，用于计算机系统中AGP功能的状态和控制。

8. 发明授权

US5914727A Valid flag for disabling allocation of accelerated graphics port memory space 失效
标题翻译：禁止分配加速图形端口内存空间的有效标志
公开(公告)号：US5914727A
公开(公告)日：1999-06-22
申请号：US925773
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F12/02 , G06F12/10 , H04N7/26 , H04N7/50 , G06F15/16
CPC分类号： G06F12/1081 , G06F12/0292 , H04N19/423 , H04N19/61
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。 AGP有效位设置为指示AGP设备是否存在。如果AGP设备不存在，则在计算机系统启动期间不会分配虚拟内存地址空间。

9. 发明授权

US6078338A Accelerated graphics port programmable memory access arbiter 失效
标题翻译：加速图形端口可编程存储器访问仲裁器
公开(公告)号：US6078338A
公开(公告)日：2000-06-20
申请号：US38412
申请日：1998-03-11
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
IPC分类号： G06F3/14 , G06F13/16 , G09G1/16 , G09G5/00 , G09G5/36
CPC分类号： G06F13/1605 , G06F3/14 , G09G3/003 , G09G5/001 , G09G5/363
摘要： A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.
摘要翻译：具有将处理器，系统存储器和外围设备代理器互连的核心逻辑芯片组的计算机系统。核心逻辑芯片组具有可编程存储器访问仲裁器，其可以被编程为优化计算机系统处理器和代理到系统存储器的访问以获得最佳计算机系统性能。存储器访问仲裁器可以针对每个系统代理进行编程。访问计数寄存器可以并入到核心逻辑芯片组中，其中每个系统代理可以由访问计数寄存器的一部分来表示。编程到访问计数寄存器的部分中的值确定在授予存储器访问的另一个代理程序之前，相关联的代理可以执行多少内存访问，以及在存储器访问期间可以传送多少个高速缓存行。

10. 发明授权

US5999743A System and method for dynamically allocating accelerated graphics port memory space 失效
标题翻译：用于动态分配加速图形端口存储空间的系统和方法
公开(公告)号：US5999743A
公开(公告)日：1999-12-07
申请号：US926422
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
IPC分类号： G06F3/14 , G09G5/36 , G09G5/39 , B06F13/00
CPC分类号： G06F3/14 , G09G5/363 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式