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1. 发明申请

US20070227656A1 Apparatus and method for confined area planarization 有权
标题翻译：限制区域平面化的装置和方法
公开(公告)号：US20070227656A1
公开(公告)日：2007-10-04
申请号：US11395881
申请日：2006-03-31
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Michael Ravkin , John Larios
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Michael Ravkin , John Larios
IPC分类号： H01L21/461 , H01L21/306
CPC分类号： H01L21/32115 , C25F7/00
摘要： A proximity head and associated method of use is provided for performing confined area planarization of a semiconductor wafer. The proximity head includes a chamber defined to maintain an electrolyte solution. A cathode is disposed within the chamber in exposure to the electrolyte solution. A cation exchange membrane is disposed over a lower opening of the chamber. A top surface of the cation exchange membrane is in direct exposure to the electrolyte solution to be maintained within the chamber. A fluid supply channel is defined to expel fluid at a location adjacent to a lower surface of the cation exchange membrane. A vacuum channel is defined to provide suction at a location adjacent to the lower surface of the cation exchange membrane, such that the fluid to be expelled from the fluid supply channel is made to flow over the lower surface of the cation exchange membrane.
摘要翻译：提供接近头和相关联的使用方法用于执行半导体晶片的限定区域平坦化。邻近头包括限定为维持电解质溶液的室。在室内暴露于电解质溶液中设置阴极。阳离子交换膜设置在室的下部开口的上方。阳离子交换膜的顶表面直接暴露于电解质溶液中以保持在室内。流体供应通道被定义为在邻近阳离子交换膜的下表面的位置排出流体。定义真空通道以在邻近阳离子交换膜的下表面的位置处提供吸力，使得要从流体供应通道排出的流体流过阳离子交换膜的下表面。

2. 发明授权

US07749893B2 Methods and systems for low interfacial oxide contact between barrier and copper metallization 有权
标题翻译：屏障和铜金属化之间的低界面氧化物接触的方法和系统
公开(公告)号：US07749893B2
公开(公告)日：2010-07-06
申请号：US11641361
申请日：2006-12-18
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

3. 发明申请

US20120205807A1 DEVICE WITH POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：具有通过一体化的线接触后端的装置
公开(公告)号：US20120205807A1
公开(公告)日：2012-08-16
申请号：US13455453
申请日：2012-04-25
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are device structures and methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了三维集成电路的器件结构和方法，该三维集成电路包括用于三维集成电路的集成的线通孔的后接后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

4. 发明授权

US07592259B2 Methods and systems for barrier layer surface passivation 有权
标题翻译：阻挡层表面钝化的方法和系统
公开(公告)号：US07592259B2
公开(公告)日：2009-09-22
申请号：US11641364
申请日：2006-12-18
申请人： Yezdi Dordi , John Boyd , Fritz Redeker , William Thie , Tiruchirapalli Arunagiri , Alex Yoon
发明人： Yezdi Dordi , John Boyd , Fritz Redeker , William Thie , Tiruchirapalli Arunagiri , Alex Yoon
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： C23C8/02 , C23C8/80 , C23C10/02 , C23C10/60 , C23C16/54 , C23C16/56 , C23C18/1601 , C23C18/1632 , C23C18/54 , C23C26/00 , C23C28/023 , C23C28/322 , C23C28/34 , C25D7/123 , C25D17/001 , H01L21/67161 , H01L21/67207 , H01L21/76855 , H01L21/76861 , H01L21/76862 , H01L21/76873
摘要： This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于制造半导体器件的方法和系统。本发明的一个方面是在用于半导体器件金属化的阻挡层上沉积间隙填充铜层的方法。在一个实施例中，该方法包括在衬底的表面上形成阻挡层，并使阻挡层经受处理条件，以便在阻挡层上形成可移除的钝化表面。该方法还包括从阻挡层去除钝化表面并将间隙填充铜层沉积到阻挡层上。本发明的另一方面是用于在用于半导体器件金属化的阻挡层上沉积铜层的集成系统。在一个实施例中，集成系统包括被配置用于阻挡层沉积和钝化表面形成的至少一个工艺模块和被配置用于钝化表面去除和沉积到阻挡层上的至少一个其它工艺模块。所述系统还包括至少一个传送模块，所述至少一个传送模块被耦合，使得所述衬底可以在所述模块之间基本上不被暴露于形成氧化物的环境

5. 发明申请

US20080315418A1 Methods of post-contact back end of line through-hole via integration 有权
标题翻译：通过一体化的后通孔后端的方法
公开(公告)号：US20080315418A1
公开(公告)日：2008-12-25
申请号：US11820811
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

6. 发明授权

US08673769B2 Methods and apparatuses for three dimensional integrated circuits 有权
标题翻译：三维集成电路的方法和装置
公开(公告)号：US08673769B2
公开(公告)日：2014-03-18
申请号：US11821051
申请日：2007-06-20
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/44 , H01L21/76898 , H01L23/48 , H01L23/481 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.
摘要翻译：提供了具有通孔的三维集成电路的制造方法和装置。本发明的一个方面是用于三维集成电路的通孔通孔的间隙填充方法。该方法包括提供具有用于通孔通孔的多个孔的半导体晶片，并且沉积保形金属层以部分填充孔以留下开孔。该方法还包括清除空隙并清洁空隙的表面，并使用干式沉积工艺填充或封闭空隙。本发明的另一方面是一种用于三维集成电路的电子设备结构。

7. 发明授权

US08133812B2 Methods and systems for barrier layer surface passivation 有权
标题翻译：阻挡层表面钝化的方法和系统
公开(公告)号：US08133812B2
公开(公告)日：2012-03-13
申请号：US12562955
申请日：2009-09-18
申请人： Yezdi Dordi , John Boyd , Fritz Redeker , William Thie , Tiruchirapalli Arunagiri , Alex Yoon
发明人： Yezdi Dordi , John Boyd , Fritz Redeker , William Thie , Tiruchirapalli Arunagiri , Alex Yoon
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： C23C8/02 , C23C8/80 , C23C10/02 , C23C10/60 , C23C16/54 , C23C16/56 , C23C18/1601 , C23C18/1632 , C23C18/54 , C23C26/00 , C23C28/023 , C23C28/322 , C23C28/34 , C25D7/123 , C25D17/001 , H01L21/67161 , H01L21/67207 , H01L21/76855 , H01L21/76861 , H01L21/76862 , H01L21/76873
摘要： This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于制造半导体器件的方法和系统。本发明的一个方面是在用于半导体器件金属化的阻挡层上沉积间隙填充铜层的方法。在一个实施例中，该方法包括在衬底的表面上形成阻挡层，并使阻挡层经受处理条件，以便在阻挡层上形成可移除的钝化表面。该方法还包括从阻挡层去除钝化表面并将间隙填充铜层沉积到阻挡层上。本发明的另一方面是用于在用于半导体器件金属化的阻挡层上沉积铜层的集成系统。在一个实施例中，集成系统包括被配置用于阻挡层沉积和钝化表面形成的至少一个工艺模块和被配置用于钝化表面去除和沉积到阻挡层上的至少一个其它工艺模块。所述系统还包括至少一个传送模块，所述至少一个传送模块被耦合，使得所述衬底可以在所述模块之间基本上不被暴露于形成氧化物的环境

8. 发明授权

US08053355B2 Methods and systems for low interfacial oxide contact between barrier and copper metallization 有权
标题翻译：屏障和铜金属化之间的低界面氧化物接触的方法和系统
公开(公告)号：US08053355B2
公开(公告)日：2011-11-08
申请号：US12828082
申请日：2010-06-30
申请人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： Fritz Redeker , John Boyd , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L21/4763
CPC分类号： C25D7/123 , C23C18/1653 , C23C28/023 , C23C28/322 , C23C28/34 , C23C28/341 , H01L21/28562 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76862 , H01L21/76873 , H01L21/76874 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于半导体器件金属化的方法和系统。本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。该方法还包括在ALD铜上沉积间隙填充铜层。本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。在一个实施例中，集成系统包括至少一个阻挡层沉积模块。该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

9. 发明申请

US20100044867A1 METHODS OF POST-CONTACT BACK END OF LINE THROUGH-HOLE VIA INTEGRATION 有权
标题翻译：通过一体化的线接触后端的方法
公开(公告)号：US20100044867A1
公开(公告)日：2010-02-25
申请号：US12613518
申请日：2009-11-05
申请人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
发明人： John Boyd , Fritz Redeker , Yezdi Dordi , Hyungsuk Alexander Yoon , Shijian Li
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/48 , H01L21/4763 , H01L21/76898 , H01L2924/14
摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
摘要翻译：提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。本发明的另一方面包括根据本发明的方法制造的三维集成电路。

10. 发明申请

US20080146025A1 Methods and systems for barrier layer surface passivation 有权
标题翻译：阻挡层表面钝化的方法和系统
公开(公告)号：US20080146025A1
公开(公告)日：2008-06-19
申请号：US11641364
申请日：2006-12-18
申请人： Yezdi Dordi , John Boyd , Fritz Redeker , William Thie , Tiruchirapalli Arunagiri , Alex Yoon
发明人： Yezdi Dordi , John Boyd , Fritz Redeker , William Thie , Tiruchirapalli Arunagiri , Alex Yoon
IPC分类号： H01L21/4763 , C25D3/38
CPC分类号： C23C8/02 , C23C8/80 , C23C10/02 , C23C10/60 , C23C16/54 , C23C16/56 , C23C18/1601 , C23C18/1632 , C23C18/54 , C23C26/00 , C23C28/023 , C23C28/322 , C23C28/34 , C25D7/123 , C25D17/001 , H01L21/67161 , H01L21/67207 , H01L21/76855 , H01L21/76861 , H01L21/76862 , H01L21/76873
摘要： This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the integrated system comprises at least one process module configured for barrier layer deposition and passivated surface formation and at least one other process module configured for passivated surface removal and deposition of copper onto the barrier layer. The system further includes at least one transfer module coupled so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.
摘要翻译：本发明涉及用于制造半导体器件的方法和系统。本发明的一个方面是在用于半导体器件金属化的阻挡层上沉积间隙填充铜层的方法。在一个实施例中，该方法包括在衬底的表面上形成阻挡层，并使阻挡层经受处理条件，以便在阻挡层上形成可移除的钝化表面。该方法还包括从阻挡层去除钝化表面并将间隙填充铜层沉积到阻挡层上。本发明的另一方面是用于在用于半导体器件金属化的阻挡层上沉积铜层的集成系统。在一个实施例中，集成系统包括被配置用于阻挡层沉积和钝化表面形成的至少一个工艺模块和被配置用于钝化表面去除和沉积到阻挡层上的至少一个其它工艺模块。所述系统还包括至少一个传送模块，所述至少一个传送模块被耦合，使得所述基板可以在所述模块之间基本上不被暴露于氧化物形成环境中。

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