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1. 发明申请

US20070025170A1 Differential and hierarchical sensing for memory circuits 失效
公开(公告)号：US20070025170A1
公开(公告)日：2007-02-01
申请号：US11190542
申请日：2005-07-27
申请人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
发明人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.

2. 发明申请

US20070223298A1 Differential and Hierarchical Sensing for Memory Circuits 有权
标题翻译：用于存储器电路的差分和分层检测
公开(公告)号：US20070223298A1
公开(公告)日：2007-09-27
申请号：US11754422
申请日：2007-05-29
申请人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
发明人： John Barth , Paul Parries , William Reohr , Matthew Wordeman
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译：存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

3. 发明申请

US20050193253A1 A Command Multiplier for Built-In-Self-Test 有权
标题翻译：用于内置自检的命令乘数
公开(公告)号：US20050193253A1
公开(公告)日：2005-09-01
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
发明人： Jonathan Fales , Gregory Fredeman , Kevin Gorman , Mark Jacunski , Toshiaki Kirihata , Alan Norris , Paul Parries , Matthew Wordeman
IPC分类号： G06F11/00 , G11C29/14 , G11C29/16
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译：公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

4. 发明申请

US20060124982A1 Low-Cost Deep Trench Decoupling Capacitor Device and Process of Manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US20060124982A1
公开(公告)日：2006-06-15
申请号：US10905094
申请日：2004-12-15
申请人： Herbert Ho , John Barth , Ramachandra Divakaruni , Wayne Ellis , Johnathan Faltermeier , Brent Anderson , Subramanian Iyer , Deok-Kee Kim , Randy Mann , Paul Parries
发明人： Herbert Ho , John Barth , Ramachandra Divakaruni , Wayne Ellis , Johnathan Faltermeier , Brent Anderson , Subramanian Iyer , Deok-Kee Kim , Randy Mann , Paul Parries
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

5. 发明申请

US20050157577A1 Concurrent refresh mode with distributed row address counters in an embedded DRAM 有权
公开(公告)号：US20050157577A1
公开(公告)日：2005-07-21
申请号：US10757846
申请日：2004-01-15
申请人： John Barth , Toshiaki Kirihata , Paul Parries
发明人： John Barth , Toshiaki Kirihata , Paul Parries
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C2207/104
摘要： A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

6. 发明申请

US20060118850A1 COLLARLESS TRENCH DRAM DEVICE 失效
标题翻译：无缝TRENCH DRAM设备
公开(公告)号：US20060118850A1
公开(公告)日：2006-06-08
申请号：US10904933
申请日：2004-12-06
申请人： Yoichi Otani , Herbert Ho , Babar Khan , Paul Parries
发明人： Yoichi Otani , Herbert Ho , Babar Khan , Paul Parries
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.
摘要翻译：本发明提供了具有最小化的垂直寄生FET泄漏的无凹槽沟槽半导体存储器件及其形成方法。

7. 发明授权

US07078247B2 Early detection of contact liner integrity by chemical reaction 失效
标题翻译：通过化学反应早期检测接触衬里的完整性
公开(公告)号：US07078247B2
公开(公告)日：2006-07-18
申请号：US10250144
申请日：2003-06-06
申请人： Lawrence Bauer, Jr. , Kenneth Giewont , Subramanian Iyer , Bosang Kim , Jeffrey Lloyd , Peter Locke , James Norum , Paul Parries , Kent Way , Kwong Hon Wong
发明人： Lawrence Bauer, Jr. , Kenneth Giewont , Subramanian Iyer , Bosang Kim , Jeffrey Lloyd , Peter Locke , James Norum , Paul Parries , Kent Way , Kwong Hon Wong
IPC分类号： H01L21/66 , H01L21/00 , H01L21/4763 , H01L21/44 , G01R31/26
CPC分类号： H01L22/24 , H01L21/31116 , Y10T436/115831
摘要： The integrity of a liner in an interconnect structure or other layer in an integrate circuit is tested in a short time by exposing the liner to a reactive gas that attacks the underlying silicon or other material behind the liner. A weak spot in the liner permits the gas to react with the silicon, which produces a visible area that can be readily identified. The test can be performed in a few hours, in contrast to a period of several months required to complete the process, package the circuit and conduct a burn-in test.
摘要翻译：在短时间内通过将衬垫暴露于攻击衬底后面的下层硅或其他材料的反应性气体来测试集成电路中的互连结构或其他层中的衬垫的完整性。衬里中的弱点允许气体与硅反应，这产生可以容易地识别的可见区域。该测试可以在几个小时内进行，与完成该过程所需的几个月的时间相比，封装电路并进行老化测试。

8. 发明申请

US20050010455A1 EARLY DETECTION OF CONTACT LINER INTEGRITY BY CHEMICAL REACTION 失效
标题翻译：通过化学反应早期检测接触衬里的整体性
公开(公告)号：US20050010455A1
公开(公告)日：2005-01-13
申请号：US10250144
申请日：2003-06-06
申请人： Lawrence Bauer , Kenneth Giewont , Subramanian Iyer , Bosang Kim , Jeffrey Lloyd , Peter Locke , James Norum , Paul Parries , Kent Way , Kwong Wong
发明人： Lawrence Bauer , Kenneth Giewont , Subramanian Iyer , Bosang Kim , Jeffrey Lloyd , Peter Locke , James Norum , Paul Parries , Kent Way , Kwong Wong
IPC分类号： H01L21/311 , H01L21/66 , G06F17/60
CPC分类号： H01L22/24 , H01L21/31116 , Y10T436/115831
摘要： The integrity of a liner in an interconnect structure or other layer in an integrate circuit is tested in a short time by exposing the liner to a reactive gas that attacks the underlying silicon or other material behind the liner. A weak spot in the liner permits the gas to react with the silicon, which produces a visible area that can be readily identified. The test can be performed in a few hours, in contrast to a period of several months required to complete the process, package the circuit and conduct a burn-in test.
摘要翻译：在短时间内通过将衬垫暴露于攻击衬底后面的下层硅或其他材料的反应性气体来测试集成电路中的互连结构或其他层中的衬垫的完整性。衬里中的弱点允许气体与硅反应，这产生可以容易地识别的可见区域。该测试可以在几个小时内进行，与完成该过程所需的几个月的时间相比，封装电路并进行老化测试。

9. 发明授权

US5976982A Methods for protecting device components from chemical mechanical polish induced defects 失效
标题翻译：保护器件部件免受化学机械抛光引起的缺陷的方法
公开(公告)号：US5976982A
公开(公告)日：1999-11-02
申请号：US884120
申请日：1997-06-27
申请人： Max G. Levy , Wolfgang Bergner , Bernhard Fiegl , George R. Goth , Paul Parries , Matthew J. Sendelbach , Tinghao T. Wang , William C. Wille , Juergen Wittmann
发明人： Max G. Levy , Wolfgang Bergner , Bernhard Fiegl , George R. Goth , Paul Parries , Matthew J. Sendelbach , Tinghao T. Wang , William C. Wille , Juergen Wittmann
IPC分类号： H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3105 , H01L21/76
CPC分类号： H01L21/31053
摘要： A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.
摘要翻译：一种用于防止对设置在台面的衬垫氮化物层下方的衬底的CMP诱导（化学机械抛光）损伤的方法。衬垫氮化物层设置在共形沉积的电介质层的下方。电介质层设置在共形沉积的多晶硅层下方。该方法包括使用CMP平坦化多晶硅层至至少介电层的表面以暴露电介质层的第一区域。该方法还包括使用第一蚀刻参数部分地蚀刻介质层的第一区域。第一蚀刻参数包括蚀刻剂源气体，其对衬垫氮化物层基本上是选择性的，以防止衬垫氮化物层即使在存在CMP缺陷的情况下被蚀刻。此外，还包括在蚀刻之后部分地通过电介质层的第一区域去除多晶硅层。

10. 发明授权

US5466636A Method of forming borderless contacts using a removable mandrel 失效
标题翻译：使用可移动心轴形成无边界触点的方法
公开(公告)号：US5466636A
公开(公告)日：1995-11-14
申请号：US946993
申请日：1992-09-17
申请人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
发明人： John E. Cronin , Carter W. Kaanta , Donald M. Kenney , Michael L. Kerbaugh , Howard S. Landis , Brian J. Machesney , Paul Parries , Rosemary A. Previti-Kelly , John F. Rembetski
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L29/417 , H01L21/44
CPC分类号： H01L27/10861 , H01L21/76838 , H01L21/76897 , H01L29/41766 , Y10S438/943
摘要： A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).
摘要翻译：一种用于使用可移除心轴（110）形成无边界触点（130,170,172）的半导体制造工艺。该方法包括将心轴沉积在设计成保护形成在基底（24）上的下面的结构（40）的下面的阻挡层（100）上。心轴由将以比阻挡层更快的速度蚀刻的材料制成，以允许心轴中的开口形成停止在阻挡层上而不穿透该层。在将形成在心轴中的第一开口（120）中的接触（130）沉积之后，形成第二开口（140），并且在其中沉积第二接触（170）。此后，移去心轴并用一层固体电介质材料（180）代替。

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