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1. 发明授权

US06903959B2 Sensing of memory integrated circuits 失效
标题翻译：感应存储器集成电路
公开(公告)号：US06903959B2
公开(公告)日：2005-06-07
申请号：US10065168
申请日：2002-09-24
申请人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
发明人： Thomas Roehr , Hans-Oliver Joachim , Joerg Wohlfahrt , Norbert Rehm
IPC分类号： G11C7/06 , G11C7/14 , G11C11/22
CPC分类号： G11C7/14 , G11C7/062 , G11C11/22
摘要： A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
摘要翻译：公开了一种在读取期间具有改进的感测的存储器IC。 IC包括使用第一和第二参考电压进行感测以补偿存在于位线真数和位线补码之间的单元之间的不对称性。第一个参考电压用于在位线真时感测单元，而第二个参考电压用于感测位线补码上的单元。

2. 发明授权

US06885597B2 Sensing test circuit 失效
标题翻译：感应测试电路
公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
申请人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
发明人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译：公开了一种用于在存储器访问期间测试差分读取信号的测试电路。测试电路耦合到一对位线。在读访问期间，所选存储单元在位线上产生差分读信号。当测试电路被激活时，差分读取信号的幅度是变化的。这使得能够容易地测试例如存储器IC中的读取信号余量。

3. 发明授权

US06999887B2 Memory cell signal window testing apparatus 失效
标题翻译：存储单元信号窗口测试仪
公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
申请人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
发明人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译：公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。在写入周期期间，首先将数据写入存储单元。在第一读取周期期间从存储器单元读取低电平信号。比较低信号和低参考信号。比较结果存储在第一存储寄存器中。在写入周期期间，第二个数据被写入存储单元。在第二读取周期期间，从存储器单元读取高电平信号。在高电平信号和高参考信号之间进行比较。比较结果存储在第二存储寄存器中。比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出高参考信号。

4. 发明授权

US06826099B2 2T2C signal margin test mode using a defined charge and discharge of BL and /BL 失效
标题翻译： 2T2C信号余量测试模式使用BL和/ BL定义充放电
公开(公告)号：US06826099B2
公开(公告)日：2004-11-30
申请号：US10301529
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
发明人： Hans-Oliver Joachim , Thomas Roehr , Joerg Wohlfahrt
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/22
摘要： A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：半导体存储器测试模式配置包括用于存储数字数据的第一电容器。第一电容器通过第一选择晶体管将单元板线连接到第一位线，该第一选择晶体管通过与字线的连接被激活。用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线，第二选择晶体管也通过与字线的连接而被激活。感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。

5. 发明申请

US20050063212A1 Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices 审中-公开
标题翻译：实现参考电路，以减少为1T1C FeRAM器件提供参考电压的参考电容的劣化
公开(公告)号：US20050063212A1
公开(公告)日：2005-03-24
申请号：US10665401
申请日：2003-09-18
申请人： Michael Jacob , Norbert Rehm , Hans-Oliver Joachim , Joerg Wohlfahrt
发明人： Michael Jacob , Norbert Rehm , Hans-Oliver Joachim , Joerg Wohlfahrt
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.
摘要翻译：半导体存储器包括用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据的第一电容器。第一个选择晶体管通过与字线的连接来激活。至少一个参考电容器为参考位线提供参考电压。连接到第一和参考位线的读出放大器测量第一和参考位线上的差分读取信号。触发触发器交替地改变存储在参考电容器上的电荷的极化。

6. 发明申请

US20050033541A1 Memory cell signal window testing apparatus 失效
标题翻译：存储单元信号窗口测试仪
公开(公告)号：US20050033541A1
公开(公告)日：2005-02-10
申请号：US10636369
申请日：2003-08-06
申请人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
发明人： Norbert Rehm , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt
IPC分类号： G06F19/00 , G11C11/22 , G11C11/4197 , G11C16/34 , G11C29/00 , G11C29/50
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译：公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。在写入周期期间，首先将数据写入存储单元。在第一读取周期期间从存储器单元读取低电平信号。比较低信号和低参考信号。比较结果存储在第一存储寄存器中。在写入周期期间，第二个数据被写入存储单元。在第二读取周期期间，从存储器单元读取高电平信号。在高电平信号和高参考信号之间进行比较。比较结果存储在第二存储寄存器中。比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出高参考信号。

7. 发明授权

US06807084B1 FeRAM memory device 失效
标题翻译： FeRAM存储器件
公开(公告)号：US06807084B1
公开(公告)日：2004-10-19
申请号：US10418734
申请日：2003-04-17
申请人： Joerg Wohlfahrt , Hans-Oliver Joachim
发明人： Joerg Wohlfahrt , Hans-Oliver Joachim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C7/20
摘要： A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.
摘要翻译：一个FeRAM存储器芯片包括用于存储数据的非易失性二元电容器存储器单元阵列5。输入引脚接收要存储的数据，以及指示存储单元数组中应存储数据的位置的地址数据。 FeRAM存储器芯片还具有用于识别外部施加的复位信号的复位单元7。复位单元7在识别到复位信号时启动复位操作，其中存储在存储单元中的数据的至少一部分被设置为预定值。

8. 发明申请

US20050047189A1 Reliable ferro fuse cell 有权
标题翻译：可靠的铁熔丝电池
公开(公告)号：US20050047189A1
公开(公告)日：2005-03-03
申请号：US10651753
申请日：2003-08-29
申请人： Roehr Thomas , Hans-Oliver Joachim , Norbert Rehm
发明人： Roehr Thomas , Hans-Oliver Joachim , Norbert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.
摘要翻译：本发明包括一个铁熔体单元，其包括电连接到一侧的板和另一侧的读出放大器的铁电存储电容器。铁电测量电容器电连接在铁电存储电容器和读出放大器之间。

9. 发明授权

US06584009B1 Memory integrated circuit with improved reliability 有权
标题翻译：内存集成电路具有提高的可靠性
公开(公告)号：US06584009B1
公开(公告)日：2003-06-24
申请号：US10103360
申请日：2002-03-21
申请人： Thomas Roehr , Hans-Oliver Joachim
发明人： Thomas Roehr , Hans-Oliver Joachim
IPC分类号： G11C1112
CPC分类号： G11C11/22 , G11C8/08
摘要： A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.
摘要翻译：描述了其中使用双电压方案来操作字线的链接存储器IC。在待机模式期间，字线保持在第一逻辑1电压电平。为了准备存储器访问，未选择的字线被驱动到升压电压，同时所选择的字线被驱动到地。第一个逻辑1电压电平小于升压电压。这降低了晶体管栅极氧化物的应力，从而提高了存储器IC的可靠性。

10. 发明授权

US06236617B1 High performance CMOS word-line driver 有权
标题翻译：高性能CMOS字线驱动
公开(公告)号：US06236617B1
公开(公告)日：2001-05-22
申请号：US09458878
申请日：1999-12-10
申请人： Louis L. Hsu , Hans-Oliver Joachim , Matthew R. Wordeman , Hing Wong
发明人： Louis L. Hsu , Hans-Oliver Joachim , Matthew R. Wordeman , Hing Wong
IPC分类号： G11C800
CPC分类号： G11C8/08
摘要： A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold. The net active power from the entire array is less than that of a conventional configuration due to the reduced voltage swing, while the number of transistors exposed to high voltage stress is reduced from 9 to 1 and the number of buffer nfets required to reduce voltage drop across an active nfet is reduced from 8 to 1.
摘要翻译：具有n组m个字线的负字形DRAM阵列暴露于一组，其中一组由组解码器电路（具有地面之间的电压摆幅和电路高电压（2v））和每组中的一个驱动器电路驱动提升的字线高电压（2.8V）大于电路高电压，其中字线驱动器电路具有包括与高阈值电压pfet串联的标准nfet的输出级，使得在激活期间，未选择的驱动器电路暴露对于升压的字线高电压通过pfet具有非常低的泄漏，而所选择的驱动器电路具有高但可容许的泄漏（2μA），因为nfet上的Vqs几乎处于nfet阈值。由于降低的电压摆幅，整个阵列的净有功功率小于传统配置的功率，而暴露于高电压应力的晶体管的数量从9减少到1，并且减少电压降所需的缓冲器数量跨越一个活跃的nfet从8减少到1。

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