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1. 发明授权

US06415378B1 Method and system for tracking the progress of an instruction in an out-of-order processor 失效
标题翻译：用于跟踪无序处理器中的指令进度的方法和系统
公开(公告)号：US06415378B1
公开(公告)日：2002-07-02
申请号：US09343359
申请日：1999-06-30
申请人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick , Joel M. Tendler
发明人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick , Joel M. Tendler
IPC分类号： G06F1100
CPC分类号： G06F11/3466
摘要： A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.
摘要翻译：提供了一种用于调试指令管线内的指令执行的方法和系统。数据处理系统中的处理器包含指令流水线单元。指令可以被标记，并且响应于指令流水线单元完成其对带标签的指令的处理，声明级完成信号。流水线处理器外部的执行监视器在执行标记指令期间监视阶段完成信号。执行监视器可以是在执行监视器的显示装置上实时显示级完成信号的逻辑分析器。可以基于诸如指令的地址的指令选择规则来选择要被标记的指令。

2. 发明授权

US06446029B1 Method and system for providing temporal threshold support during performance monitoring of a pipelined processor 有权
标题翻译：用于在流水线处理器的性能监视期间提供临时阈值支持的方法和系统
公开(公告)号：US06446029B1
公开(公告)日：2002-09-03
申请号：US09343449
申请日：1999-06-30
申请人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick
发明人： Joel Roger Davidson , Judith K. Laurens , Alexander Erik Mericas , Kevin F. Reick
IPC分类号： G06F1500
CPC分类号： G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for monitoring the performance of a instruction pipeline is provided. The processor may contain a performance monitor for monitoring for the occurrence of an event within a data processing system. An event to be monitored may be specified through software control, and the occurrence of the specified event is monitored during the execution of an instruction in the execution pipeline of the processor. A particular instruction may be specified to execute within a threshold time for each stage of the instruction pipeline. The specified event may be the completion of a single tagged instruction beyond the specified threshold interval for a stage of the instruction pipeline. The performance monitor may contain a number of counters for counting multiple occurrences of specified events during the execution of multiple instructions, in which case the specified events may be the completion of tagged instructions beyond a threshold interval for any stage of the multiple stages of the execution pipeline. As the instruction moves through the processor, the performance monitor collects the events and provides the events for optimization analysis.
摘要翻译：提供了一种用于监视指令流水线性能的方法和系统。处理器可以包含用于监视数据处理系统内的事件发生的性能监视器。可以通过软件控制指定要监视的事件，并且在执行处理器的执行流水线中的指令期间监视指定事件的发生。可以指定特定指令以在指令流水线的每个阶段的阈值时间内执行。指定的事件可以是超出指令流水线阶段的指定阈值间隔的单个标记指令的完成。性能监视器可以包含多个计数器，用于在执行多个指令期间对多次发生的指定事件进行计数，在这种情况下，指定事件可以是执行多个执行阶段的任何阶段的阈值间隔之外的已标记指令的完成管道。当指令移动通过处理器时，性能监视器收集事件并提供事件进行优化分析。

3. 发明授权

US06629170B1 Method and apparatus for a byte lane selectable performance monitor bus 失效
标题翻译：用于字节通道可选性能监视总线的方法和装置
公开(公告)号：US06629170B1
公开(公告)日：2003-09-30
申请号：US09436110
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
发明人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
IPC分类号： G06F1300
CPC分类号： G06F11/348 , G06F11/349 , G06F2201/88
摘要： A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.
摘要翻译：多级字节通道可选择总线。在优选实施例中，性能监视模式中的总线包括多个字节通道和选择机构。选择机制从多个信号中获取希望被监视的那些信号的子集，并将该子集信号放置在输入到PMU的字节通道上。可能被监视的多个信号的数量大于字节通道的数量，并且也大于PMU计数器的数量。

4. 发明授权

US06574727B1 Method and apparatus for instruction sampling for performance monitoring and debug 失效
标题翻译：用于性能监控和调试的指令采样方法和装置
公开(公告)号：US06574727B1
公开(公告)日：2003-06-03
申请号：US09435069
申请日：1999-11-04
申请人： Joel Roger Davidson , John Edward Derrick , Alexander Erik Mericas
发明人： Joel Roger Davidson , John Edward Derrick , Alexander Erik Mericas
IPC分类号： G06F900
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3857 , G06F11/348 , G06F2201/88
摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.
摘要翻译：提出了一种在数据处理系统中选择流水线处理器内要监视的指令的方法和装置。获取多个指令，并且将多个指令与至少一个匹配条件进行匹配，以生成符合抽样要求的指令。匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。可以使用通过选择过程伴随指令的匹配位来标记匹配的指令。然后对符合抽样要求的指令进行采样以产生采样指令。采样指令可以通过指令执行过程伴随指令的采样位进行标记，以便在流水线处理器中执行时监视采样指令。

5. 发明授权

US06539502B1 Method and apparatus for identifying instructions for performance monitoring in a microprocessor 失效
标题翻译：用于识别用于微处理器中的性能监视的指令的方法和装置
公开(公告)号：US06539502B1
公开(公告)日：2003-03-25
申请号：US09436109
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Michael Stephen Floyd , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/88
摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V0 and V1, are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V0 and V1 pair(s). For each bit in the instruction word, the corresponding bit in V0 and V1 are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.
摘要翻译：提出了一种在流水线处理器内选择要监视的指令的方法和装置。存储在控制寄存器中的一对或多对匹配值被分配用于指令采样或指令匹配。这些对，称为V0和V1，一起用于过滤用于采样或指令匹配的指令。在提取或解码阶段，将指令字逐位比较为V0和V1对。对于指令字中的每个位，V0和V1中的相应位用于确定是否存在匹配。如果指令字中的每个位都产生匹配，则该指令有资格进行采样。如果任何位位置不匹配，则说明不符合条件。响应于确定该指令有资格进行采样，可以监视该指令的执行。

6. 发明授权

US06530042B1 Method and apparatus for monitoring the performance of internal queues in a microprocessor 失效
标题翻译：用于监视微处理器内部队列性能的方法和装置
公开(公告)号：US06530042B1
公开(公告)日：2003-03-04
申请号：US09436108
申请日：1999-11-08
申请人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F11/3409 , G06F11/3452 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and apparatus for monitoring an internal queue within a processor, such as an instruction completion table or instruction re-order buffer, is presented. The performance monitoring unit of the processor contains multiple counters, and each counter counts occurrences of specified events. An internal queue of the processor may be specified to be monitored. A count of event signals indicating a successful allocation request for an entry in the internal queue is divided by a count of event signals indicating a passage of units of time to obtain the average rate for allocation requests for queue entries in the specified internal queue. A count of event signals indicating an occupation of a specific entry in the internal queue during a unit of time is divided by a count of event signals indicating an allocation of a specific entry in the internal queue to obtain the average time spent in the internal queue. An average number of entries in the internal queue is computed as a product of the average rate for allocation requests for queue entries and the average time spent in the internal queue. An event signal that indicates failure of an allocation request for an entry in the internal queue may be monitored.
摘要翻译：提出了一种用于监视处理器内的内部队列的方法和装置，例如指令完成表或指令重新排序缓冲器。处理器的性能监视单元包含多个计数器，每个计数器计数指定事件的出现次数。可以指定处理器的内部队列进行监视。指示对内部队列中的条目的成功分配请求的事件信号的计数除以指示通过时间单位的事件信号的计数，以获得指定的内部队列中的队列条目的分配请求的平均速率。指示在时间单位内对内部队列中的特定条目的占用的事件信号的计数除以表示内部队列中的特定条目的分配的事件信号的计数，以获得在内部队列中花费的平均时间。内部队列中的平均条目数量计算为队列条目的分配请求的平均速率和在内部队列中花费的平均时间的乘积。可以监视指示内部队列中的条目的分配请求失败的事件信号。

7. 发明授权

US06718403B2 Hierarchical selection of direct and indirect counting events in a performance monitor unit 有权
标题翻译：在性能监视器单元中分层选择直接和间接计数事件
公开(公告)号：US06718403B2
公开(公告)日：2004-04-06
申请号：US09734116
申请日：2000-12-11
申请人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06E300
CPC分类号： G06F13/4217 , G06F11/3409 , G06F11/3466 , G06F11/349 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into sub-groups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals that are connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.
摘要翻译：公开了一种包括性能监视器单元的微处理器。性能监视器单元包括一组性能监视计数器和一组相应的控制电路和可编程控制寄存器。性能监视器单元从处理器的功能单元接收第一组事件信号。第一组事件中的每一个直接从适当的功能单元路由到性能监视器单元。性能监视器单元进一步接收至少第二组事件信号。在一个实施例中，经由处理器的性能监视总线接收第二组事件信号。性能监视器总线通常是可以从处理器的任何功能单元接收信号的共享总线。功能单元可以包括复用电路，其确定哪个功能单元具有共享总线的掌握。而性能监视器单元通常能够监视任何其计数器中的直接事件信号，间接事件信号可被选择性地路由到计数器。共享总线可以被划分成子组或字节通道，其中字节通道被选择性地路由到一组性能监视计数器。控制寄存器的状态可以确定在相应计数器中监视的事件。在一个实施例中，控制寄存器提供连接到一个或多个多路复用器的选择输入的一组信号。多路复用器接收多个事件信号，并且基于其选择信号的状态，将接收的事件信号中的一个路由到相应的性能监视计数器。选择信号的指定状态可能导致禁用相应的计数器或使计数器能够对系统时钟周期进行计数，而不是任何性能事件。

8. 发明授权

US06550002B1 Method and system for detecting a flush of an instruction without a flush indicator 失效
标题翻译：用于检测没有冲洗指示器的指令冲洗的方法和系统
公开(公告)号：US06550002B1
公开(公告)日：2003-04-15
申请号：US09435067
申请日：1999-11-04
申请人： Joel Roger Davidson , Hung Oui Le , Alexander Erik Mericas
发明人： Joel Roger Davidson , Hung Oui Le , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F9/3836 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F11/3466
摘要： A method and system for detecting flushed instructions without a flush indicator is provided. In order to monitor the flushing of an instruction in an instruction pipeline of a processor, an instruction is selected as a sampled instruction and the progress of the sampled instruction through the instruction pipeline is monitored. Upon selection of an instruction as a sampled instruction, a countdown value is initialized to a value equal to the maximum number of instructions within the instruction pipeline, and as instructions complete, the countdown value is decremented. If progress of the sampled instruction is detected as the instruction moves through the instruction pipeline, the countdown value is reinitialized. If the countdown value reaches zero, then a flush of the sampled instruction from the instruction pipeline is presumed, and an indication that the sampled instruction has been flushed is generated. In response to the indication that the sampled instruction has been flushed, a subsequent instruction may be selected as a subsequently sampled instruction.
摘要翻译：提供一种用于检测没有冲洗指示器的冲洗指令的方法和系统。为了监视处理器的指令流水线中的指令的刷新，选择指令作为采样指令，并监视通过指令流水线的采样指令的进度。在选择指令作为采样指令时，将倒数值初始化为等于指令流水线内最大指令数的值，并且随着指令的完成，递减计数值。如果指令在指令流水线中移动，则检测到采样指令的进度，则重新初始化倒数值。如果倒计时值为零，则假定来自指令流水线的采样指令的刷新，并且产生已经刷新了采样指令的指示。响应于采样指令已被刷新的指示，随后的指令可以被选择为随后采样的指令。

9. 发明授权

US06725307B1 Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system 失效
标题翻译：用于通过分布式多总线多处理器系统中的数据功能与地址和控制功能的物理分离来控制数据传输的方法和系统
公开(公告)号：US06725307B1
公开(公告)日：2004-04-20
申请号：US09404280
申请日：1999-09-23
申请人： Manuel Joseph Alvarez, II , Joel Roger Davidson , Sanjay Raghunath Deshpande , Peter Dau Geiger , Lawrence Joseph Powell , Praveen S. Reddy
发明人： Manuel Joseph Alvarez, II , Joel Roger Davidson , Sanjay Raghunath Deshpande , Peter Dau Geiger , Lawrence Joseph Powell , Praveen S. Reddy
IPC分类号： G06F100
CPC分类号： G06F15/17381 , G06F12/0813 , G06F12/0831
摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, e.g. buses that support a high number of data pins, the node controller may be implemented such that the functionality for its address paths and data paths are implemented in physically separate components, chips, or circuitry, such as a node data controller or a node address controller. In this case, commands may be sent from the node address controller to the node data controller to control the flow of data through a node.
摘要翻译：提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。由于可能由大型总线引起的引脚限制，例如支持大量数据引脚的总线，可以实现节点控制器，使得其地址路径和数据路径的功能在物理上分离的组件，芯片或电路中实现，诸如节点数据控制器或节点地址控制器。在这种情况下，命令可以从节点地址控制器发送到节点数据控制器，以控制通过节点的数据流。

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