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1. 发明授权

US06629170B1 Method and apparatus for a byte lane selectable performance monitor bus 失效
标题翻译：用于字节通道可选性能监视总线的方法和装置
公开(公告)号：US06629170B1
公开(公告)日：2003-09-30
申请号：US09436110
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
发明人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
IPC分类号： G06F1300
CPC分类号： G06F11/348 , G06F11/349 , G06F2201/88
摘要： A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.
摘要翻译：多级字节通道可选择总线。在优选实施例中，性能监视模式中的总线包括多个字节通道和选择机构。选择机制从多个信号中获取希望被监视的那些信号的子集，并将该子集信号放置在输入到PMU的字节通道上。可能被监视的多个信号的数量大于字节通道的数量，并且也大于PMU计数器的数量。

2. 发明授权

US06539502B1 Method and apparatus for identifying instructions for performance monitoring in a microprocessor 失效
标题翻译：用于识别用于微处理器中的性能监视的指令的方法和装置
公开(公告)号：US06539502B1
公开(公告)日：2003-03-25
申请号：US09436109
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Michael Stephen Floyd , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/88
摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V0 and V1, are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V0 and V1 pair(s). For each bit in the instruction word, the corresponding bit in V0 and V1 are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.
摘要翻译：提出了一种在流水线处理器内选择要监视的指令的方法和装置。存储在控制寄存器中的一对或多对匹配值被分配用于指令采样或指令匹配。这些对，称为V0和V1，一起用于过滤用于采样或指令匹配的指令。在提取或解码阶段，将指令字逐位比较为V0和V1对。对于指令字中的每个位，V0和V1中的相应位用于确定是否存在匹配。如果指令字中的每个位都产生匹配，则该指令有资格进行采样。如果任何位位置不匹配，则说明不符合条件。响应于确定该指令有资格进行采样，可以监视该指令的执行。

3. 发明授权

US07472315B2 Method of seamlessly integrating thermal event information data with performance monitor data 有权
标题翻译：将热事件信息数据与性能监视数据无缝集成的方法
公开(公告)号：US07472315B2
公开(公告)日：2008-12-30
申请号：US11054292
申请日：2005-02-09
申请人： Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella
发明人： Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.
摘要翻译：提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

4. 发明授权

US07711994B2 Apparatus, system and computer program product for seamlessly integrating thermal event information data with performance monitor data 失效
标题翻译：用于将热事件信息数据与性能监视数据无缝集成的装置，系统和计算机程序产品
公开(公告)号：US07711994B2
公开(公告)日：2010-05-04
申请号：US12131070
申请日：2008-05-31
申请人： Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella
发明人： Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.
摘要翻译：提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

5. 发明授权

US07620801B2 Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor 失效
标题翻译：方法随机或伪随机，无偏差，选择微处理器性能分析指令
公开(公告)号：US07620801B2
公开(公告)日：2009-11-17
申请号：US11055848
申请日：2005-02-11
申请人： James Wilson Bishop , Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella , Dung Quoc Nguyen , Philip Lee Vitale
发明人： James Wilson Bishop , Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella , Dung Quoc Nguyen , Philip Lee Vitale
IPC分类号： G06F9/30
CPC分类号： G06F11/3409 , G06F11/3466 , G06F11/349 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.
摘要翻译：一种用于伪随机，无偏差的方法，用于在微处理器中选择用于标记的指令。响应于从指令高速缓存读取指令，将与指令相关联的指令标记与线性反馈移位寄存器（LFSR）中的伪随机生成值进行比较。如果指令标签与LFSR中的值相匹配，则表示指令是标记指令的标记位与指令一起发送到执行单元。响应于性能监视器的指示，LFSR中的值在选择下一个要标记的指令之前递增。如果该值等于预定的素数增量，则该值被重置为全部值，以避免与正在执行的码流的任何谐波。在接收到标记指令之后，执行单元将所标记的位与所选择的事件相结合，并将标记的事件报告给性能监视器。

6. 发明申请

US20080244330A1 APPARATUS, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SEAMLESSLY INTEGRATING THERMAL EVENT INFORMATION DATA WITH PERFORMANCE MONITOR DATA 失效
标题翻译：装置，系统和计算机程序产品，用于无缝集成具有性能监视数据的热事件信息数据
公开(公告)号：US20080244330A1
公开(公告)日：2008-10-02
申请号：US12131070
申请日：2008-05-31
申请人： Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella
发明人： Michael Stephen Floyd , Alexander Erik Mericas , Robert Dominick Mirabella
IPC分类号： G06F11/30
CPC分类号： G06F11/00
摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.
摘要翻译：提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

7. 发明授权

US08261276B2 Power-efficient thread priority enablement 有权
标题翻译：高效的线程优先级启用
公开(公告)号：US08261276B2
公开(公告)日：2012-09-04
申请号：US12059576
申请日：2008-03-31
申请人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
发明人： Pradip Bose , Alper Buyuktosunoglu , Richard James Eickemeyer , Susan Elizabeth Eisen , Michael Stephen Floyd , Hans Mikael Jacobson , Jeffrey R. Summers
IPC分类号： G06F9/46 , G06F9/00 , G06F13/28 , G06F1/32
CPC分类号： G06F9/4893 , Y02D10/24
摘要： A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.
摘要翻译：一种用于控制在线程切换控制寄存器中的指令获取和调度线程优先级设置的机制，用于减少平衡刷新的发生和调度刷新以提高同时多线程数据处理系统的功率性能。为了实现处理器的目标功率效率模式，说明性实施例从较高级系统控制器接收指令或命令以设置处理器的当前功耗。说明性实施例确定了处理器的目标功率效率模式。一旦确定了目标功率模式，则说明性实施例更新用于执行线程的线程切换控制寄存器中的线程优先级设置，以控制平衡冲突推测和调度冲销推测以实现目标功率效率模式。

8. 发明授权

US07979750B2 Synchronizing triggering of multiple hardware trace facilities using an existing system bus 失效
标题翻译：使用现有系统总线同步触发多个硬件跟踪工具
公开(公告)号：US07979750B2
公开(公告)日：2011-07-12
申请号：US12144422
申请日：2008-06-23
申请人： Ra'ed Mohammad Al-Omari , Michael Stephen Floyd , Paul Frank Lecocq
发明人： Ra'ed Mohammad Al-Omari , Michael Stephen Floyd , Paul Frank Lecocq
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.
摘要翻译：在用于使用现有总线触发多个硬件跟踪设备的数据处理系统中公开了一种方法，装置和计算机程序产品。多个硬件跟踪设备包括第一个硬件跟踪设备和第二个硬件跟踪设备。数据处理系统包括第一处理器，其包括第一硬件跟踪设备和利用系统总线耦合在一起的第一处理单元，以及包括第二硬件跟踪设备的第二处理器和利用系统耦合在一起的第二处理单元总线。当处理器处于正常的非跟踪模式时，利用系统总线在第一和第二处理单元之间传送信息，其中信息根据标准系统总线协议被格式化。触发事件使用相同的标准系统总线传输到硬件跟踪设备，触发事件也根据标准系统总线协议进行格式化。

9. 发明申请

US20080141000A1 INTELLIGENT SMT THREAD HANG DETECT TAKING INTO ACCOUNT SHARED RESOURCE CONTENTION/BLOCKING 有权
标题翻译：智能SMT螺纹连接检测进入帐户共享资源内容/阻塞
公开(公告)号：US20080141000A1
公开(公告)日：2008-06-12
申请号：US12033385
申请日：2008-02-19
申请人： Michael Stephen Floyd , Larry Scott Leitner
发明人： Michael Stephen Floyd , Larry Scott Leitner
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/3842 , G06F9/3867 , G06F11/0715 , G06F11/0721 , G06F11/0757 , G06F11/1407
摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.
摘要翻译：执行监视以检测挂起状况。一个定时器被设置为基于核心挂起限制来检测挂起。如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可能会增加到更长的内存挂起限制。响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

10. 发明授权

US07305586B2 Accessing and manipulating microprocessor state 失效
标题翻译：访问和操作微处理器状态
公开(公告)号：US07305586B2
公开(公告)日：2007-12-04
申请号：US10424485
申请日：2003-04-25
申请人： Richard William Doing , Michael Stephen Floyd , Ronald Nick Kalla , John Wesley Ward, III
发明人： Richard William Doing , Michael Stephen Floyd , Ronald Nick Kalla , John Wesley Ward, III
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.
摘要翻译：微处理器包括外部可访问端口和连接到端口的串行通信总线。处理器的执行流水线包括将管道耦合到总线的流水线卫星电路。该卫星使外部代理可以通过串行总线直接向管线提供指令。专用寄存器和寄存器卫星电路将寄存器耦合到通信总线。在执行指令期间，执行流水线可以访问专用寄存器。以这种方式，卫星电路使外部代理能够访问架构状态。当处理器的系统时钟保持有效时，通信总线可以访问卫星。在一个实施例中，流水线卫星访问解码级的“下游”流水线，使得可能被“冲撞”到流水线中的指令集不限于解码级可以产生的一组指令。

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