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1. 发明授权

US06629170B1 Method and apparatus for a byte lane selectable performance monitor bus 失效
标题翻译：用于字节通道可选性能监视总线的方法和装置
公开(公告)号：US06629170B1
公开(公告)日：2003-09-30
申请号：US09436110
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
发明人： Joel Roger Davidson , Michael Stephen Floyd , Paul Joseph Jordan , Judith E. K. Laurens , Alexander Erik Mericas , Kevin F. Reick
IPC分类号： G06F1300
CPC分类号： G06F11/348 , G06F11/349 , G06F2201/88
摘要： A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.
摘要翻译：多级字节通道可选择总线。在优选实施例中，性能监视模式中的总线包括多个字节通道和选择机构。选择机制从多个信号中获取希望被监视的那些信号的子集，并将该子集信号放置在输入到PMU的字节通道上。可能被监视的多个信号的数量大于字节通道的数量，并且也大于PMU计数器的数量。

2. 发明授权

US06539502B1 Method and apparatus for identifying instructions for performance monitoring in a microprocessor 失效
标题翻译：用于识别用于微处理器中的性能监视的指令的方法和装置
公开(公告)号：US06539502B1
公开(公告)日：2003-03-25
申请号：US09436109
申请日：1999-11-08
申请人： Joel Roger Davidson , Michael Stephen Floyd , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Michael Stephen Floyd , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/88
摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V0 and V1, are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V0 and V1 pair(s). For each bit in the instruction word, the corresponding bit in V0 and V1 are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.
摘要翻译：提出了一种在流水线处理器内选择要监视的指令的方法和装置。存储在控制寄存器中的一对或多对匹配值被分配用于指令采样或指令匹配。这些对，称为V0和V1，一起用于过滤用于采样或指令匹配的指令。在提取或解码阶段，将指令字逐位比较为V0和V1对。对于指令字中的每个位，V0和V1中的相应位用于确定是否存在匹配。如果指令字中的每个位都产生匹配，则该指令有资格进行采样。如果任何位位置不匹配，则说明不符合条件。响应于确定该指令有资格进行采样，可以监视该指令的执行。

3. 发明授权

US06718403B2 Hierarchical selection of direct and indirect counting events in a performance monitor unit 有权
标题翻译：在性能监视器单元中分层选择直接和间接计数事件
公开(公告)号：US06718403B2
公开(公告)日：2004-04-06
申请号：US09734116
申请日：2000-12-11
申请人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06E300
CPC分类号： G06F13/4217 , G06F11/3409 , G06F11/3466 , G06F11/349 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into sub-groups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals that are connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.
摘要翻译：公开了一种包括性能监视器单元的微处理器。性能监视器单元包括一组性能监视计数器和一组相应的控制电路和可编程控制寄存器。性能监视器单元从处理器的功能单元接收第一组事件信号。第一组事件中的每一个直接从适当的功能单元路由到性能监视器单元。性能监视器单元进一步接收至少第二组事件信号。在一个实施例中，经由处理器的性能监视总线接收第二组事件信号。性能监视器总线通常是可以从处理器的任何功能单元接收信号的共享总线。功能单元可以包括复用电路，其确定哪个功能单元具有共享总线的掌握。而性能监视器单元通常能够监视任何其计数器中的直接事件信号，间接事件信号可被选择性地路由到计数器。共享总线可以被划分成子组或字节通道，其中字节通道被选择性地路由到一组性能监视计数器。控制寄存器的状态可以确定在相应计数器中监视的事件。在一个实施例中，控制寄存器提供连接到一个或多个多路复用器的选择输入的一组信号。多路复用器接收多个事件信号，并且基于其选择信号的状态，将接收的事件信号中的一个路由到相应的性能监视计数器。选择信号的指定状态可能导致禁用相应的计数器或使计数器能够对系统时钟周期进行计数，而不是任何性能事件。

4. 发明授权

US06530042B1 Method and apparatus for monitoring the performance of internal queues in a microprocessor 失效
标题翻译：用于监视微处理器内部队列性能的方法和装置
公开(公告)号：US06530042B1
公开(公告)日：2003-03-04
申请号：US09436108
申请日：1999-11-08
申请人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
发明人： Joel Roger Davidson , Judith E. K. Laurens , Alexander Erik Mericas
IPC分类号： G06F1130
CPC分类号： G06F11/3409 , G06F11/3452 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and apparatus for monitoring an internal queue within a processor, such as an instruction completion table or instruction re-order buffer, is presented. The performance monitoring unit of the processor contains multiple counters, and each counter counts occurrences of specified events. An internal queue of the processor may be specified to be monitored. A count of event signals indicating a successful allocation request for an entry in the internal queue is divided by a count of event signals indicating a passage of units of time to obtain the average rate for allocation requests for queue entries in the specified internal queue. A count of event signals indicating an occupation of a specific entry in the internal queue during a unit of time is divided by a count of event signals indicating an allocation of a specific entry in the internal queue to obtain the average time spent in the internal queue. An average number of entries in the internal queue is computed as a product of the average rate for allocation requests for queue entries and the average time spent in the internal queue. An event signal that indicates failure of an allocation request for an entry in the internal queue may be monitored.
摘要翻译：提出了一种用于监视处理器内的内部队列的方法和装置，例如指令完成表或指令重新排序缓冲器。处理器的性能监视单元包含多个计数器，每个计数器计数指定事件的出现次数。可以指定处理器的内部队列进行监视。指示对内部队列中的条目的成功分配请求的事件信号的计数除以指示通过时间单位的事件信号的计数，以获得指定的内部队列中的队列条目的分配请求的平均速率。指示在时间单位内对内部队列中的特定条目的占用的事件信号的计数除以表示内部队列中的特定条目的分配的事件信号的计数，以获得在内部队列中花费的平均时间。内部队列中的平均条目数量计算为队列条目的分配请求的平均速率和在内部队列中花费的平均时间的乘积。可以监视指示内部队列中的条目的分配请求失败的事件信号。

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