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1. 发明授权

US07962877B2 Port assignment in hierarchical designs by abstracting macro logic 有权
标题翻译：通过抽象宏逻辑在分层设计中的端口分配
公开(公告)号：US07962877B2
公开(公告)日：2011-06-14
申请号：US12185943
申请日：2008-08-05
申请人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
发明人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.
摘要翻译：当执行端口分配时，减少问题复杂度的方法通过抽象宏中的本地连接来维持相对较高质量的端口分配。这是为了网络长度，拥塞以及时序而完成的。宏的内部网表被抽象出来，可以以有效的方式完成外部互连的优化。描述了三个层次的抽象。第一级优化顶级互连，第二级优化顶级和宏互连，而第三级优化顶级时间。

2. 发明授权

US08762919B2 Circuit macro placement using macro aspect ratio based on ports 失效
标题翻译：使用基于端口的宏宽高比的电路宏放置
公开(公告)号：US08762919B2
公开(公告)日：2014-06-24
申请号：US12949998
申请日：2010-11-19
申请人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
发明人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).
摘要翻译：通过基于由宏端口权重值，宏端口排序中的任何一个组成的标准修改可修改的轮廓形状宏的轮廓来操纵电子电路设计的固定轮廓形状和可修改轮廓形状的随机逻辑宏。宏观融合约束或宏观逻辑深度，并将结果宏放置在集成电路（芯片）的位置。

3. 发明申请

US20110289468A1 Circuit Macro Placement Using Macro Aspect Ratio Based on Ports 失效
标题翻译：基于端口的宏观纵横比的电路宏放置
公开(公告)号：US20110289468A1
公开(公告)日：2011-11-24
申请号：US12949998
申请日：2010-11-19
申请人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
发明人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).
摘要翻译：通过基于由宏端口权重值，宏端口排序中的任何一个组成的标准修改可修改的轮廓形状宏的轮廓来操纵电子电路设计的固定轮廓形状和可修改轮廓形状的随机逻辑宏。宏观融合约束或宏观逻辑深度，并将结果宏放置在集成电路（芯片）的位置。

4. 发明申请

US20100037198A1 PORT ASSIGNMENT IN HIERARCHICAL DESIGNS BY ABSTRACTING MACRO LOGIC 有权
标题翻译：通过提取宏观逻辑在分层设计中的端口分配
公开(公告)号：US20100037198A1
公开(公告)日：2010-02-11
申请号：US12185943
申请日：2008-08-05
申请人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
发明人： Joachim Keinert , Juergen Koehl , Thomas Ludwig
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing.
摘要翻译：当执行端口分配时，减少问题复杂度的方法通过抽象宏中的本地连接来维持相对较高质量的端口分配。这是为了网络长度，拥塞以及时序而完成的。宏的内部网表被抽象出来，可以以有效的方式完成外部互连的优化。描述了三个层次的抽象。第一级优化顶级互连，第二级优化顶级和宏互连，而第三级优化顶级时间。

5. 发明授权

US08522187B2 Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program product 失效
标题翻译：方法和数据处理系统优化电路设计，数据处理程序和计算机程序产品的性能
公开(公告)号：US08522187B2
公开(公告)日：2013-08-27
申请号：US13311651
申请日：2011-12-06
申请人： Niels Fricke , Bernd Kemmler , Juergen Koehl , Karsten Muuss , Matthias Ringe
发明人： Niels Fricke , Bernd Kemmler , Juergen Koehl , Karsten Muuss , Matthias Ringe
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505 , G06F2217/78 , G06F2217/84
摘要： A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization.
摘要翻译：公开了一种优化电路设计性能的方法。该方法包括为电路的每个电路元件设计可用的设计参数选项; 将电路设计和设计参数选项转换为线性规划模型; 确定线性规划模型的解决方案; 并且基于产生电路元件列表的解决方案，其中设计参数需要改变为不同的选项以实现性能优化。

6. 发明申请

US20120216016A1 INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE 有权
标题翻译：指导性调度方法，以提高处理器性能
公开(公告)号：US20120216016A1
公开(公告)日：2012-08-23
申请号：US13459128
申请日：2012-04-28
申请人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
发明人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30141 , G06F8/443 , G06F9/3012 , G06F9/3855 , G06F17/505 , G06F2217/68
摘要： A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
摘要翻译：一种处理器指令调度器，其包括使用用于处理器架构的优化模型的优化引擎，其具有：从处理器的设计和表示优化目标和约束的代码流以及代码流生成优化引擎的优化模型的装置，其中所述处理器具有至少两个执行管道和至少两个寄存器，并且其中所述设计包括用于处理器指令等待时间和执行管道的数据，并且其中所述代码流包括具有相应寄存器选择的处理器指令; 以及重新排序装置，用于通过重新排序代码流，从优化引擎为优化模型提供的优化解决方案，从代码流生成优化代码流，从而实现给定约束条件下优化目标的最优值，而不影响操作代码流的结果。

7. 发明授权

US08234594B2 Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：冗余微环结构用于集成电路物理设计过程及其形成方法
公开(公告)号：US08234594B2
公开(公告)日：2012-07-31
申请号：US11552225
申请日：2006-10-24
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种集成电路，包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线和位于距离第二线的第一距离的第四线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔大致轴向对准第一通孔。第三通过在第四线的第二位置连接第三和第四导线。在第二位置连接第一和第四导线的第四通孔，第四通孔与第三通孔大致轴向对齐。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

8. 发明授权

US08056037B2 Method for validating logical function and timing behavior of a digital circuit decision 有权
标题翻译：用于验证数字电路决策的逻辑功能和时序特性的方法
公开(公告)号：US08056037B2
公开(公告)日：2011-11-08
申请号：US12233169
申请日：2008-09-18
申请人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
发明人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.
摘要翻译：本发明涉及一种在基于周期的验证环境中验证数字电路设计的正确逻辑功能和定时特性的方法。该方法包括以下步骤：提供数字电路设计的VHDL描述，执行逻辑合成，其中将VHDL描述转变为逻辑门的设计实现，以及创建包括数字电路设计的元件的网表，以及所述元件之间的连接。该方法包括以下步骤：向至少一个透明存储元件提供变换脚本，其中所述透明存储元件表示所述数字电路设计内的路径延迟，用所述至少一个透明存储元件创建新的网表，运行验证，并从逻辑和定时的角度检查新的网表是否干净。

9. 发明授权

US07984394B2 Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same 有权
标题翻译：用于集成电路物理设计过程中使用的冗余微环结构的设计结构及其形成方法
公开(公告)号：US07984394B2
公开(公告)日：2011-07-19
申请号：US11955580
申请日：2007-12-13
申请人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
发明人： Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
摘要翻译：一种用于集成电路的设计结构，该集成电路包括第一级布线轨道的第一线，第二级布线轨道的第二线，第三级布线轨道的第三线，以及位于第一距离处的第四线第二根电线在第二级线路上。第一通孔在第二导线的第一位置连接第一和第二导线。第二通孔在第一位置处连接第二和第三导线，第二通孔基本上与第一通孔轴向对准。第三通过在第四线的第二位置连接第三和第四导线。第四通孔在第二位置处连接第一和第四导线，第四通孔基本上与第三通孔轴向对准。第二，第三和第四通孔以及第三和第四导线形成第一和第二导线之间的路径，该路径对于第一通孔是冗余的。

10. 发明申请

US20090083684A1 Method for Violating the Logical Function and Timing Behavior of a Digital Circuit Decision 有权
标题翻译：违反数字电路决策的逻辑功能和定时行为的方法
公开(公告)号：US20090083684A1
公开(公告)日：2009-03-26
申请号：US12233169
申请日：2008-09-18
申请人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
发明人： Juergen Koehl , Walter Pietschmann , Juergen Saalmueller , Norbert Schumacher , Volker Urban , Joerg Walter
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing (10) a VHDL description of the digital circuit design, performing (12) a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating (14) a netlist including the elements of the digital circuit design and the connections between said elements. Said method comprises the further steps of providing (28) a transformation script with at least one transparent storage element (40; 54), wherein said transparent storage element (40; 54) represents a path delay within the digital circuit design, creating (30) a new netlist with the at least one transparent storage elements (40; 54), running (20) a verification, and checking, if the new netlist is clean from a logical and timing point of view.
摘要翻译：本发明涉及一种在基于周期的验证环境中验证数字电路设计的正确逻辑功能和定时特性的方法。所述方法包括以下步骤：提供（10）数字电路设计的VHDL描述，执行（12）逻辑合成，其中VHDL描述在逻辑门方面变成设计实现，并且创建（14）网表包括数字电路设计的元件和所述元件之间的连接。所述方法包括以下步骤：提供具有至少一个透明存储元件（40; 54）的转换脚本（28），其中所述透明存储元件（40; 54）表示数字电路设计内的路径延迟，创建（30 ）具有至少一个透明存储元件（40; 54）的新网表，运行（20）验证，并且如果所述新网表从逻辑和定时观点清洁，则检查。

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