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1. 发明授权

US08972961B2 Instruction scheduling approach to improve processor performance 有权
标题翻译：指令调度方法来提高处理器性能
公开(公告)号：US08972961B2
公开(公告)日：2015-03-03
申请号：US13105024
申请日：2011-05-11
申请人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
发明人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
IPC分类号： G06F9/45 , G06F9/38 , G06F17/50
CPC分类号： G06F9/30141 , G06F8/443 , G06F9/3012 , G06F9/3855 , G06F17/505 , G06F2217/68
摘要： A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
摘要翻译：一种处理器指令调度器，其包括使用用于处理器架构的优化模型的优化引擎，其具有：从处理器的设计和表示优化目标和约束的代码流以及代码流生成优化引擎的优化模型的装置，其中所述处理器具有至少两个执行管道和至少两个寄存器，并且其中所述设计包括用于处理器指令等待时间和执行管道的数据，并且其中所述代码流包括具有相应寄存器选择的处理器指令; 以及重新排序装置，用于通过重新排序代码流，从优化引擎为优化模型提供的优化解决方案，从代码流生成优化代码流，从而实现给定约束条件下优化目标的最优值，而不影响操作代码流的结果。

2. 发明授权

US08935685B2 Instruction scheduling approach to improve processor performance 有权
公开(公告)号：US08935685B2
公开(公告)日：2015-01-13
申请号：US13459128
申请日：2012-04-28
申请人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
发明人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
IPC分类号： G06F9/45 , G06F9/38 , G06F17/50
CPC分类号： G06F9/30141 , G06F8/443 , G06F9/3012 , G06F9/3855 , G06F17/505 , G06F2217/68
摘要： A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

3. 发明申请

US20110289297A1 INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE 有权
标题翻译：指导性调度方法，以提高处理器性能
公开(公告)号：US20110289297A1
公开(公告)日：2011-11-24
申请号：US13105024
申请日：2011-05-11
申请人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
发明人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30141 , G06F8/443 , G06F9/3012 , G06F9/3855 , G06F17/505 , G06F2217/68
摘要： A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
摘要翻译：一种处理器指令调度器，其包括使用用于处理器架构的优化模型的优化引擎，其具有：从处理器的设计和表示优化目标和约束的代码流以及代码流生成优化引擎的优化模型的装置，其中所述处理器具有至少两个执行管道和至少两个寄存器，并且其中所述设计包括用于处理器指令等待时间和执行管道的数据，并且其中所述代码流包括具有相应寄存器选择的处理器指令; 以及重新排序装置，用于通过重新排序代码流，从优化引擎为优化模型提供的优化解决方案，从代码流生成优化代码流，从而实现给定约束条件下优化目标的最优值，而不影响操作代码流的结果。

4. 发明申请

US20120216016A1 INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE 有权
标题翻译：指导性调度方法，以提高处理器性能
公开(公告)号：US20120216016A1
公开(公告)日：2012-08-23
申请号：US13459128
申请日：2012-04-28
申请人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
发明人： Juergen Koehl , Jens Leenstra , Philipp Panitz , Hans Schlenker
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30141 , G06F8/443 , G06F9/3012 , G06F9/3855 , G06F17/505 , G06F2217/68
摘要： A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.
摘要翻译：一种处理器指令调度器，其包括使用用于处理器架构的优化模型的优化引擎，其具有：从处理器的设计和表示优化目标和约束的代码流以及代码流生成优化引擎的优化模型的装置，其中所述处理器具有至少两个执行管道和至少两个寄存器，并且其中所述设计包括用于处理器指令等待时间和执行管道的数据，并且其中所述代码流包括具有相应寄存器选择的处理器指令; 以及重新排序装置，用于通过重新排序代码流，从优化引擎为优化模型提供的优化解决方案，从代码流生成优化代码流，从而实现给定约束条件下优化目标的最优值，而不影响操作代码流的结果。

5. 发明授权

US09207995B2 Mechanism to speed-up multithreaded execution by register file write port reallocation 有权
标题翻译：通过注册文件写入端口重新分配来加快多线程执行的机制
公开(公告)号：US09207995B2
公开(公告)日：2015-12-08
申请号：US13170003
申请日：2011-06-27
申请人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
发明人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
IPC分类号： G06F9/30 , G06F9/52 , G06F9/38
CPC分类号： G06F9/52 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30189 , G06F9/3891
摘要： Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file.
摘要翻译：可以使用各种系统和过程来加速多线程执行。在某些实现中，系统和过程可以包括使用第一寄存器堆的第一写入端口将与第一寄存器堆相关联的第一组执行单元的结果写入第一寄存器堆的能力，以及第二组的写入结果使用第二寄存器文件的第一写入端口将与第二寄存器文件相关联的执行单元分配到第二寄存器堆中。系统，装置和过程还可以包括以共享寄存器文件模式将第二组执行单元的结果连接到第一寄存器堆的第二写入端口并以分割寄存器文件模式连接的能力，将第一组执行单元的一部分的结果提供给第一注册文件的第二写入端口。

6. 发明授权

US09164725B2 Apparatus and method for calculating an SHA-2 hash function in a general purpose processor 有权
标题翻译：用于在通用处理器中计算SHA-2哈希函数的装置和方法
公开(公告)号：US09164725B2
公开(公告)日：2015-10-20
申请号：US13181678
申请日：2011-07-13
申请人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
发明人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
IPC分类号： G06F7/00 , H04L9/32
CPC分类号： G06F7/00 , H04L9/3239 , H04L2209/125
摘要： Various systems, apparatuses, processes, and/or products may be used to calculate an SHA-2 hash function in a general-purpose processor. In some implementations, a system, apparatus, process, and/or product may include the ability to calculate at least one SHA-2 sigma function by using an execution unit adapted for performing a processor instruction, the execution unit including an integrated circuit primarily designed for calculating the SHA-2 sigma function(s), and calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function(s). In certain implementations, the calculation of the SHA-2 sigma function(s) can be performed by the integrated circuit within a single instruction, allowing for a faster calculation of the SHA-2 hash function.
摘要翻译：可以使用各种系统，装置，处理和/或产品来计算通用处理器中的SHA-2哈希函数。在一些实现中，系统，装置，过程和/或产品可以包括通过使用适于执行处理器指令的执行单元来计算至少一个SHA-2σ功能的能力，所述执行单元包括主要设计的集成电路用于计算SHA-2西格玛函数，以及基于σ函数计算具有处理器的通用硬件处理组件的SHA-2哈希函数。在某些实现中，SHA-2西格玛函数的计算可以由单个指令中的集成电路执行，从而可以更快地计算SHA-2哈希函数。

7. 发明申请

US20120150933A1 METHOD AND DATA PROCESSING UNIT FOR CALCULATING AT LEAST ONE MULTIPLY-SUM OF TWO CARRY-LESS MULTIPLICATIONS OF TWO INPUT OPERANDS, DATA PROCESSING PROGRAM AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：方法和数据处理单元，用于计算两个输入运算的两次无关多项式的多项式，数据处理程序和计算机程序产品
公开(公告)号：US20120150933A1
公开(公告)日：2012-06-14
申请号：US13183639
申请日：2011-07-15
申请人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
发明人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
IPC分类号： G06F7/52 , G06F7/50
CPC分类号： G06F7/53 , G06F2207/382 , G06F2207/3828
摘要： Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.
摘要翻译：可以使用各种系统，装置，处理和程序来计算两个输入操作数的两次无进位乘法的乘法和。在特定实施方案中，系统，装置，过程和程序可以包括使用用于输入操作数的输入数据总线和用于总体计算结果的输出数据总线的能力，每个总线包括2n位的宽度，其中n是大于1的整数。系统，装置，过程和程序还可以计算用于较低级别的分层结构的两个输入操作数的无进位乘法，并且计算用于更高级别的至少一个乘法和至少一个中间乘数和基于较低级别的无进位乘法的结构级别。可以根据所使用的全部宽度的输出数据总线，根据操作模式，输出一定数量的乘数作为总计算结果。

8. 发明授权

US08903882B2 Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product 有权
标题翻译：用于计算两个输入操作数，数据处理程序和计算机程序产品的两个无进位乘法的至少一个乘法和方法和数据处理单元
公开(公告)号：US08903882B2
公开(公告)日：2014-12-02
申请号：US13183639
申请日：2011-07-15
申请人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
发明人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
IPC分类号： G06F7/38 , G06F7/53
CPC分类号： G06F7/53 , G06F2207/382 , G06F2207/3828
摘要： Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.
摘要翻译：可以使用各种系统，装置，处理和程序来计算两个输入操作数的两次无进位乘法的乘法和。在特定实施方案中，系统，装置，过程和程序可以包括使用用于输入操作数的输入数据总线和用于总体计算结果的输出数据总线的能力，每个总线包括2n位的宽度，其中n是大于1的整数。系统，装置，过程和程序还可以计算用于较低级别的分层结构的两个输入操作数的无进位乘法，并且计算用于更高级别的至少一个乘法和至少一个中间乘数和基于较低级别的无进位乘法的结构级别。可以根据所使用的全部宽度的输出数据总线，根据操作模式，输出一定数量的乘数作为总计算结果。

9. 发明申请

US20120128149A1 APPARATUS AND METHOD FOR CALCULATING AN SHA-2 HASH FUNCTION IN A GENERAL PURPOSE PROCESSOR 有权
标题翻译：在一般用途处理器中计算SHA-2 HASH功能的装置和方法
公开(公告)号：US20120128149A1
公开(公告)日：2012-05-24
申请号：US13181678
申请日：2011-07-13
申请人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
发明人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
IPC分类号： H04L9/28
CPC分类号： G06F7/00 , H04L9/3239 , H04L2209/125
摘要： Various systems, apparatuses, processes, and/or products may be used to calculate an SHA-2 hash function in a general-purpose processor. In some implementations, a system, apparatus, process, and/or product may include the ability to calculate at least one SHA-2 sigma function by using an execution unit adapted for performing a processor instruction, the execution unit including an integrated circuit primarily designed for calculating the SHA-2 sigma function(s), and calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function(s). In certain implementations, the calculation of the SHA-2 sigma function(s) can be performed by the integrated circuit within a single instruction, allowing for a faster calculation of the SHA-2 hash function.
摘要翻译：可以使用各种系统，装置，处理和/或产品来计算通用处理器中的SHA-2哈希函数。在一些实现中，系统，装置，过程和/或产品可以包括通过使用适于执行处理器指令的执行单元来计算至少一个SHA-2σ功能的能力，所述执行单元包括主要设计的集成电路用于计算SHA-2西格玛函数，以及基于σ函数计算具有处理器的通用硬件处理组件的SHA-2哈希函数。在某些实现中，SHA-2西格玛函数的计算可以由单个指令中的集成电路执行，从而可以更快地计算SHA-2哈希函数。

10. 发明申请

US20120110271A1 MECHANISM TO SPEED-UP MULTITHREADED EXECUTION BY REGISTER FILE WRITE PORT REALLOCATION 有权
标题翻译：通过注册文件写入端口重新加速进行多机化执行的机制
公开(公告)号：US20120110271A1
公开(公告)日：2012-05-03
申请号：US13170003
申请日：2011-06-27
申请人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
发明人： Maarten J. Boersma , Markus Kaltenbach , Jens Leenstra , Tim Niggemeier , Philipp Oehler , Philipp Panitz
IPC分类号： G06F12/00
CPC分类号： G06F9/52 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30189 , G06F9/3891
摘要： Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file.
摘要翻译：可以使用各种系统和过程来加速多线程执行。在某些实现中，系统和过程可以包括使用第一寄存器堆的第一写入端口将与第一寄存器堆相关联的第一组执行单元的结果写入第一寄存器堆的能力，以及第二组的写入结果使用第二寄存器文件的第一写入端口将与第二寄存器文件相关联的执行单元分配到第二寄存器堆中。系统，装置和过程还可以包括以共享寄存器文件模式将第二组执行单元的结果连接到第一寄存器堆的第二写入端口并以分割寄存器文件模式连接的能力，将第一组执行单元的一部分的结果提供给第一注册文件的第二写入端口。

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