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1. 发明授权

US6027996A Method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing 失效
标题翻译：使用化学机械抛光对预金属介电层进行平面化的方法
公开(公告)号：US6027996A
公开(公告)日：2000-02-22
申请号：US885173
申请日：1997-06-30
申请人： Jiunh-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Jiunh-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/3105 , H01L21/4763
CPC分类号： H01L21/31053
摘要： A method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing, in order to alleviate the problem of resistance reduction when making products having poly-loads, includes providing a semiconductor substrate with a semiconductor component formed thereabove. A pre-metal dielectric layer is formed above the semiconductor substrate. Thereafter, the pre-metal dielectric layer is planarized using chemical-mechanical polishing. Next, a silicon-rich oxide layer, that has a characteristic gettering property which can be used to compensate for the weakening of the gettering ability of the pre-metal dielectric layer, due to the wearing out of the layer in a chemical-mechanical polishing operation, is formed above the pre-metal dielectric layer.
摘要翻译：使用化学机械抛光来平坦化预金属介电层的方法为了减轻制造具有多重负载的产品时的电阻降低的问题，包括提供半导体衬底上形成有半导体元件的方法。在半导体衬底上形成预金属介电层。此后，使用化学机械抛光对金属前介电层进行平面化。接下来，由于化学机械抛光中的层的磨损，具有特征吸气特性的富硅氧化物层可用于补偿预金属介电层的吸杂能力的弱化操作，形成在预金属介电层的上方。

2. 发明授权

US5885894A Method of planarizing an inter-layer dielectric layer 失效
标题翻译：平面化层间电介质层的方法
公开(公告)号：US5885894A
公开(公告)日：1999-03-23
申请号：US882303
申请日：1997-06-25
申请人： Jiunh-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Jiunh-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： C23C16/40 , H01L21/3105 , H01L21/316
CPC分类号： H01L21/02164 , C23C16/401 , H01L21/02129 , H01L21/022 , H01L21/02274 , H01L21/31053 , H01L21/31612
摘要： A method of planarizing an inter-layer dielectric layer includes using a high density plasma chemical vapor deposition method to deposit an undoped dielectric, which increases the polishing efficiency in a subsequent chemical-mechanical polishing operation, and eliminates the need for a high temperature densifying treatment for planarization. A chemical-mechanical polishing operation is used to planarize the inter-layer dielectric.
摘要翻译：平面化层间电介质层的方法包括使用高密度等离子体化学气相沉积方法沉积未掺杂的电介质，这在随后的化学机械抛光操作中提高了抛光效率，并且不需要高温致密化处理用于平坦化。使用化学机械抛光操作来平坦化层间电介质。

3. 发明授权

US08062536B2 High density plasma chemical vapor deposition process 有权
标题翻译：高密度等离子体化学气相沉积工艺
公开(公告)号：US08062536B2
公开(公告)日：2011-11-22
申请号：US12729234
申请日：2010-03-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , Wen-Bin Shieh , Juan-Yuan Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/467 , H01L21/32 , H01L21/308 , H01L21/762
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

4. 发明授权

US07378740B2 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US07378740B2
公开(公告)日：2008-05-27
申请号：US11196038
申请日：2005-08-02
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7681 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

5. 发明申请

US20060099824A1 High density plasma chemical vapor deposition process 有权
公开(公告)号：US20060099824A1
公开(公告)日：2006-05-11
申请号：US11315904
申请日：2005-12-22
申请人： Chih-Chien Liu , Ta-Shan Tseng , W.B. Shieh , J.Y. Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Ta-Shan Tseng , W.B. Shieh , J.Y. Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/31
CPC分类号： H01L21/02112 , H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/31612 , H01L21/32136 , H01L21/32139 , H01L21/76834 , H01L21/76837 , H01L21/76838
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

6. 发明授权

US6100205A Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process 失效
标题翻译：使用高密度等离子体化学气相沉积工艺，具有低介电常数的金属间介电层形成
公开(公告)号：US6100205A
公开(公告)日：2000-08-08
申请号：US958828
申请日：1997-10-28
申请人： Chih-Chien Liu , J. Y. Wu , Tsang-Jung Lin , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , J. Y. Wu , Tsang-Jung Lin , Water Lur , Shih-Wei Sun
IPC分类号： C23C16/04 , C23C16/40 , C23C16/50 , H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , C23C16/50 , H01L21/022 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76801
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积介电层。执行第一HDPCVD步骤以在布线上形成布线之间的间隙中的第一介电层。执行PECVD步骤以将电介质材料沉积在第一介电层上并且在间隙内并限定开口。执行第二HDPCVD步骤，并且由PECVD步骤限定的开口被第三介电层覆盖。该方法允许以相当可控的方式在相邻的金属布线之间形成空气填充的空隙，这允许选择空隙的形状和空隙的顶部的精确定位。此外，空隙通过比典型的更致密和更耐用的材料密封。

7. 发明授权

US6020258A Method for unlanded via etching using etch stop 失效
标题翻译：使用蚀刻停止法进行无衬底通孔蚀刻的方法
公开(公告)号：US6020258A
公开(公告)日：2000-02-01
申请号：US982266
申请日：1997-12-01
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76834 , Y10S438/97
摘要： A multilevel interconnect structure is formed in a manner that reduces the problems associated with the formation and subsequent filling of unlanded vias. A first level wiring line is provided on the surface of an interlayer dielectric. The upper surface and sidewalls of the first level wiring line are covered with an etch stop material that is different from the intermetal dielectric used to separate the first level of wiring line from upper levels of wiring lines. The intermetal dielectric layer is deposited over the first level wiring line and a via is etched through the intermetal dielectric to expose the etch stop material above the wiring line, with the via etch stopping on the etch stop material. Etch stop material is removed to expose a portion of the upper surface of the wiring line and a metal plug is formed within the via and then an upper level wiring line is formed in contact with the metal plug.
摘要翻译：形成多层互连结构，其方法是减少与无衬层通孔的形成和随后填充有关的问题。在层间电介质的表面上设置一级布线。第一级布线的上表面和侧壁被不同于用于将第一级布线与上层布线分开的金属间电介质的蚀刻停止材料覆盖。金属间电介质层沉积在第一层布线上，并通过金属间电介质蚀刻通孔，以使布线线上方的蚀刻停止材料露出，同时蚀刻停止材料上的通孔蚀刻停止。去除蚀刻停止材料以露出布线的上表面的一部分，并且在通孔内形成金属塞，然后形成与金属塞接触的上层布线。

8. 发明授权

US5968610A Multi-step high density plasma chemical vapor deposition process 失效
标题翻译：多级高密度等离子体化学气相沉积工艺
公开(公告)号：US5968610A
公开(公告)日：1999-10-19
申请号：US959407
申请日：1997-10-28
申请人： Chih-Chien Liu , Kuen-Jian Chen , Yu-Hao Chen , J. Y. Wu , Water Lur , Shih-Wei Sun
发明人： Chih-Chien Liu , Kuen-Jian Chen , Yu-Hao Chen , J. Y. Wu , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/316 , H01L21/762 , B05D3/06 , H01L21/76
CPC分类号： H01L21/02112 , H01L21/02274 , H01L21/02304 , H01L21/31612 , H01L21/76224
摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.
摘要翻译：在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括使用高密度等离子体化学气相沉积（HDPCVD）沉积三个氧化物层。进行第一HDPCVD步骤，同时保持衬底不偏差以在线和间隙中形成氧化物层。衬底被偏置的第二HDPCVD步骤在第一氧化物层上沉积第二氧化物层。在第二HDPCVD步骤期间，发生一些蚀刻，并且去除第一氧化物层的一部分。以比用第二步骤更大的蚀刻和溅射速率进行第三HDPCVD步骤，以完成用电介质材料填充间隙。第一氧化物层用于在第三步骤期间保护下面的结构免受蚀刻损伤。布线之间的间隙可以填充介电材料，而不会形成空隙，即使对于高纵横比的间隙也是如此。

9. 发明授权

US5960299A Method of fabricating a shallow-trench isolation structure in integrated circuit 失效
标题翻译：在集成电路中制造浅沟槽隔离结构的方法
公开(公告)号：US5960299A
公开(公告)日：1999-09-28
申请号：US181466
申请日：1998-10-28
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure in an integrated circuit, which can prevent the occurrence of microscratches in the oxide plugs of the STI structure, thus further preventing the occurrence of a bridging effect and short-circuits between the circuit components that are intended to be electrically isolated by the STI structure. This method is characterized by the use of a laser annealing process to remove the microscratches that formed on the top surface of the oxide plugs during the chemical-mechanical polishing (CMP) process used to remove the upper part of the oxide layer to form the oxide plugs This method can therefore prevent the occurrence of a bridging effect and short-circuits due to the forming of the microscratches that would otherwise occur in the prior art.
摘要翻译：提供了一种用于在集成电路中制造浅沟槽隔离（STI）结构的半导体制造方法，其可以防止在STI结构的氧化物塞中发生微细纹理，从而进一步防止桥接效应的发生，要通过STI结构电隔离的电路元件之间的电路。该方法的特征在于使用激光退火工艺来除去在用于去除氧化物层的上部以形成氧化物的化学机械抛光（CMP）工艺期间在氧化物塞的顶表面上形成的微观尺度堵塞该方法因此可以防止桥接效应的发生和由于形成在现有技术中将会出现的微纹理造成的短路。

10. 发明授权

US5874353A Method of forming a self-aligned silicide device 失效
标题翻译：形成自对准硅化物器件的方法
公开(公告)号：US5874353A
公开(公告)日：1999-02-23
申请号：US927321
申请日：1997-09-11
申请人： Tony Lin , Water Lur , Shih-Wei Sun
发明人： Tony Lin , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L29/4925 , H01L29/4941
摘要： A method of forming self-aligned silicide devices which includes providing a silicon substrate having shallow trench isolation regions for defining a device area formed therein; then, forming sequentially a gate oxide layer, a polysilicon layer, a first titanium nitride layer, a titanium silicide layer, a second titanium nitride layer and a silicon nitride layer over the substrate. After a gate electrode is etched out from the above layers, a titanium layer is deposited over the device, and then a self-aligned titanium silicide layer is formed using a heating process. The use of a titanium silicide layer having protective top and bottom titanium nitride layers, compared with a single tungsten silicide layer in a conventional method, provides for a self-aligned silicide device having a rather low gate resistance; being free from narrow width effect of a titanium self-aligned silicide layer; is applicable to self-aligned contact window processes, and avoids the cross-diffusion of doped ions in the polysilicon layer of a dual gate electrode having a tungsten polycide layer.
摘要翻译：一种形成自对准硅化物器件的方法，其包括提供具有浅沟槽隔离区域的硅衬底，用于限定其中形成的器件区域; 然后在衬底上依次形成栅氧化层，多晶硅层，第一氮化钛层，硅化钛层，第二氮化钛层和氮化硅层。在从上述层蚀刻出栅电极之后，在器件上沉积钛层，然后使用加热工艺形成自对准硅化钛层。与常规方法中的单个硅化钨层相比，使用具有保护性顶部和底部氮化钛层的硅化钛层提供具有相当低的栅极电阻的自对准硅化物器件; 没有钛自对准硅化物层的窄宽度效应; 适用于自对准接触窗工艺，并避免掺杂离子在具有钨多硅化物层的双栅电极的多晶硅层中的交叉扩散。

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