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    • 3. 发明授权
      US07271408B2 Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors 失效
    • Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors
    • 用于精确测量半导体单元晶体管中的漏电流的半导体器件测试图案和相关方法
    • US07271408B2
    • 2007-09-18
    • US10796672
    • 2004-03-09
    • Young-pil Kim , Beom-jun Jin
    • Young-pil Kim , Beom-jun Jin
    • H01L23/58
    • H01L27/10882 , H01L22/32 , H01L27/108 , H01L27/10814 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
    • Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.
    • 提供半导体器件测试图案，其包括在半导体衬底上的字线和在半导体衬底中具有第一杂质掺杂区和第二杂质掺杂区的有源区。 第一自对准接触焊盘电连接到第一杂质掺杂区域，第一直接接触电连接到第一自对准接触焊盘。 第一位线电连接到第一直接触点，并且第一探针焊盘电连接到第一位线。 测试图案还包括电连接到第二杂质掺杂区的第二自对准接触焊盘和电连接到第二自对准接触焊盘的第二直接接触。 第二导电线电连接到第二直接接触，第二探测焊盘电连接到第二导线。 这些测试图案可用于测量半导体器件的单元晶体管中的漏电流。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5981324A Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein 失效
    • Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein
    • 在其中形成具有存储单元阵列和外围电路的集成电路的方法
    • US5981324A
    • 1999-11-09
    • US956584
    • 1997-10-23
    • Young-woo Seo , Young-pil Kim , Myeon-koo Kang , Won-shik Lee
    • Young-woo Seo , Young-pil Kim , Myeon-koo Kang , Won-shik Lee
    • H01L21/8239 , H01L21/8242
    • H01L27/10844 , H01L27/1052
    • Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.
    • 形成其中具有存储单元阵列的集成电路及其外围电路的方法包括以下步骤：为存储单元阵列中的晶体管选择性地形成更多的轻掺杂源极和漏极区域。 这些更轻掺杂的源极和漏极区域被设计为在离子注入中具有较少的晶体缺陷，使得与其耦合的存储电容器具有改善的刷新特性。 优选的方法包括以下步骤：在半导体衬底的存储单元部分中形成第一导电类型的第一阱区域（例如，P型）和在半导体衬底延伸的外围电路部分中的第一导电类型的第二阱区域 邻近存储单元部分。 然后使用常规技术分别在第一和第二阱区上形成第一和第二绝缘栅电极。 然后使用第一和第二绝缘栅电极作为植入掩模，将第一导电类型的第一掺杂剂以第一剂量水平注入第一阱区和第二阱区。 然后这些掺杂剂被扩散以形成与第一和第二绝缘栅电极相邻的轻掺杂源极和漏极区。 然后使用自对准技术将第二导电类型的第二掺杂剂以大于第一剂量水平的第二剂量水平选择性地植入第二阱区。 然而，这些掺杂剂优选不被植入第一阱区。 然后将这些第二掺杂剂扩散到第二源/漏区。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US6043537A Embedded memory logic device using self-aligned silicide and manufacturing method therefor 失效
    • Embedded memory logic device using self-aligned silicide and manufacturing method therefor
    • 使用自对准硅化物的嵌入式存储器逻辑器件及其制造方法
    • US6043537A
    • 2000-03-28
    • US016092
    • 1998-01-30
    • In-kyun Jun , Young-pil Kim , Hyung-moo Park , Myeon-koo Kang
    • In-kyun Jun , Young-pil Kim , Hyung-moo Park , Myeon-koo Kang
    • H01L27/10 , H01L21/8229 , H01L21/8242 , H01L21/8244 , H01L27/01
    • H01L27/10894 , H01L27/11 , H01L27/10873 , H01L27/10888
    • The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.
    • 具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。 存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。 根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。 在第一区域上形成第一栅电极。 掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。 第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。 此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。 金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5714401A Semiconductor device capacitor manufactured by forming stack with multiple material layers without conductive layer therebetween 失效
    • Semiconductor device capacitor manufactured by forming stack with multiple material layers without conductive layer therebetween
    • 通过形成具有多个材料层的叠层而不具有导电层的半导体器件电容器
    • US5714401A
    • 1998-02-03
    • US521985
    • 1995-08-31
    • Young-pil Kim , Jong-bok Kim , Won-sik Lee , Yong-hee Lee
    • Young-pil Kim , Jong-bok Kim , Won-sik Lee , Yong-hee Lee
    • H01L21/302 , H01L21/3065 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
    • H01L27/10852 , H01L27/10817
    • A method is provided for manufacturing a capacitor of a semiconductor device. First, an insulating layer, an etching barrier layer, a first material layer and a second material layer are sequentially stacked on a semiconductor substrate on which a field oxide layer and a gate electrode are formed, and predetermined portions of the stacked layers are sequentially etched to form a contact hole exposing the substrate. Then, a first conductive layer is formed on thge whole surface of the resultant structure having the contact hole. Subsequently, a storage electrode pattern is formed by patterning the first conductive layer and etching the second material layer. Then, a second conductive layer is formed on the whole surface of the resultant structure so as to cover the storage electrode pattern and the first material layer. Thereafter, the second conductive layer is etched to expose the upper surface of the storage electrode pattern. Therefore, the capacitor manufacturing process, particularly, the etching process, is simplified, and can be applied to a capacitor having a COB structure.
    • 提供一种用于制造半导体器件的电容器的方法。 首先，将绝缘层，蚀刻阻挡层，第一材料层和第二材料层依次层叠在其上形成有场氧化物层和栅电极的半导体基板上，并且层叠的预定部分被依次蚀刻 以形成露出衬底的接触孔。 然后，在具有接触孔的所得结构的整个表面上形成第一导电层。 随后，通过图案化第一导电层并蚀刻第二材料层来形成存储电极图案。 然后，在所得结构的整个表面上形成第二导电层，以覆盖存储电极图案和第一材料层。 此后，蚀刻第二导电层以暴露存储电极图案的上表面。 因此，电容器制造工艺，特别是蚀刻工艺被简化，并且可以应用于具有COB结构的电容器。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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