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1. 发明申请

US20120003799A1 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers 有权
标题翻译：制造具有Si和SiGe外延层的半导体器件的方法
公开(公告)号：US20120003799A1
公开(公告)日：2012-01-05
申请号：US13137733
申请日：2011-09-08
申请人： Jin-bum Kim , Si-young Choi , Hyung-Ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-Ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.
摘要翻译：制造半导体器件的方法可以包括在第一有源区（P沟道FET）上形成第一层，在第二有源区（N沟道FET）上形成第二层，第一和第二层包括硅锗（SiGe ）外延层，其顺序堆叠在硅（Si）外延层上，在包括暴露第一层的SiGe外延层的第一下部区域的层间绝缘膜中形成第一接触孔，在层间绝缘膜中形成第二接触孔，所述第二接触孔包括穿过第二层的SiGe外延层并暴露第二层的Si外延层的第二下部区域，在第一下部区域中形成包括锗（Ge）的第一金属硅化物膜，形成不包括第二金属硅化物膜的第二金属硅化物膜 Ge在第二下部区域同时形成第一金属硅化物膜。

2. 发明授权

US08039902B2 Semiconductor devices having Si and SiGe epitaxial layers 有权
标题翻译：具有Si和SiGe外延层的半导体器件
公开(公告)号：US08039902B2
公开(公告)日：2011-10-18
申请号：US12591249
申请日：2009-11-13
申请人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; first and second contact pad layers each including silicon (Si) and SiGe epitaxial layers on the source and drain regions the SiGe epitaxial layers being sequentially stacked on the Si epitaxial layers; an interlayer insulating film; a first metal silicide film on the SiGe epitaxial layer of the P-channel transistor and a second metal silicide film on the Si epitaxial layer of the N-channel transistor; and contact plugs on the first and second metal silicide films.
摘要翻译：半导体器件包括具有第一和第二有源区的衬底; 与第一有源区相关并且包括源区和漏区中的至少一个的P沟道晶体管; 与所述第二有源区相关并且包括所述源极和漏极区中的至少一个的N沟道场效应晶体管; 第一和第二接触焊盘层，每个包括在源极和漏极区上的硅（Si）和SiGe外延层，SiGe外延层顺序堆叠在Si外延层上; 层间绝缘膜; 在P沟道晶体管的SiGe外延层上的第一金属硅化物膜和在N沟道晶体管的Si外延层上的第二金属硅化物膜; 以及在第一和第二金属硅化物膜上的接触插塞。

3. 发明申请

US20100123198A1 Semiconductor devices and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100123198A1
公开(公告)日：2010-05-20
申请号：US12591249
申请日：2009-11-13
申请人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/772
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same. One or more of the semiconductor devices include a substrate having first and second active regions; a P-channel field-effect transistor associated with the first active region and including at least one of the source and drain regions; a N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; a first contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the P-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; a second contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the N-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; an interlayer insulating film formed on the P-channel and the N-channel field-effect transistors and including first and second contact holes, wherein the first contact hole includes a first lower region that exposes the SiGe epitaxial layer of the first contact pad layer and the second contact hole includes a second lower region that penetrates through the SiGe epitaxial layer of the second contact pad layer to expose the Si epitaxial layer of the second contact pad layer; first and second metal silicide films formed respectively in the first and second lower regions of the contact holes; and contact plugs formed on the first and second metal silicide films and filled in the first and second contact holes.
摘要翻译：提供具有低电阻触点的半导体器件及其制造方法。一个或多个半导体器件包括具有第一和第二有源区的衬底; 与所述第一有源区相关并且包括所述源极和漏极区中的至少一个的P沟道场效应晶体管; 与所述第二有源区相关并且包括所述源极和漏极区中的至少一个的N沟道场效应晶体管; 在所述P沟道场效应晶体管的所述源极和漏极区的至少一个上包括硅（Si）和SiGe外延层的第一接触焊盘层，所述SiGe外延层顺序地堆叠在所述Si外延层上; 在所述N沟道场效应晶体管的所述源极和漏极区的至少一个上包括硅（Si）和SiGe外延层的第二接触焊盘层，所述SiGe外延层顺序地堆叠在所述Si外延层上; 形成在P沟道和N沟道场效应晶体管上并且包括第一和第二接触孔的层间绝缘膜，其中第一接触孔包括暴露第一接触焊盘层的SiGe外延层的第一下部区域和第二接触孔包括穿过第二接触焊盘层的SiGe外延层的第二下部区域，以暴露第二接触焊盘层的Si外延层; 第一和第二金属硅化物膜分别形成在接触孔的第一和第二下部区域中; 以及形成在第一和第二金属硅化物膜上的接触塞，并填充在第一和第二接触孔中。

4. 发明授权

US08324043B2 Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers 有权
公开(公告)号：US08324043B2
公开(公告)日：2012-12-04
申请号：US13137733
申请日：2011-09-08
申请人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
发明人： Jin-bum Kim , Si-young Choi , Hyung-ik Lee , Ki-hong Kim , Yong-koo Kyoung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L21/76855 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.

5. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

6. 发明授权

US07755133B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

7. 发明申请

US20110127530A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20110127530A1
公开(公告)日：2011-06-02
申请号：US13025011
申请日：2011-02-10
申请人： YONG-HOON SON , Si-young Choi , Jong-wook Lee
发明人： YONG-HOON SON , Si-young Choi , Jong-wook Lee
IPC分类号： H01L29/772
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.
摘要翻译：一种制造半导体集成电路的方法包括在半导体衬底上形成第一电介质层，图案化第一电介质层以形成第一图案化电介质层，在第一图案化电介质层上形成非单晶种子层，的种子层以形成图案化种子层，在第一图案化介电层和图案化种子层上形成第二介电层，去除第二介电层的部分以形成第二图案化电介质层，将图案化种子层照射到单个将图案化种子层结晶，去除第一图案化电介质层和第二图案化电介质层的部分，使得单结晶种子层相对于第一和/或第二图案化电介质层在垂直方向上突出，并且形成与单晶活性图案接触的栅电极。

8. 发明授权

US07785985B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07785985B2
公开(公告)日：2010-08-31
申请号：US12133772
申请日：2008-06-05
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.
摘要翻译：可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层。所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成在第一沟槽和第二沟槽中的掩埋绝缘层。掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

9. 发明申请

US20090311846A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成低温分离区的方法
公开(公告)号：US20090311846A1
公开(公告)日：2009-12-17
申请号：US12466178
申请日：2009-05-14
申请人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

10. 发明申请

US20080073690A1 Flash memory device including multilayer tunnel insulator and method of fabricating the same 审中-公开
标题翻译：包括多层隧道绝缘体的闪存器件及其制造方法
公开(公告)号：US20080073690A1
公开(公告)日：2008-03-27
申请号：US11589789
申请日：2006-10-31
申请人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Dong-kak Lee
发明人： Sung-kweon Baek , Sang-ryol Yang , Si-young Choi , Bon-young Koo , Ki-hyun Hwang , Dong-kak Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L29/40114 , H01L29/42324 , H01L29/513
摘要： A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate disposed on the intergate insulation layer.
摘要翻译：闪存器件可以包括设置在衬底上的下部隧道绝缘层，设置在下部隧道绝缘层上的上部隧道绝缘层，设置在上部隧道绝缘层上的浮动栅极，设置在浮动栅极上的栅极间绝缘层; 以及设置在隔间绝缘层上的控制栅极。

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