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1. 发明授权

US5965927A Integrated circuit having an opening for a fuse 有权
标题翻译：具有用于保险丝的开口的集成电路
公开(公告)号：US5965927A
公开(公告)日：1999-10-12
申请号：US157513
申请日：1998-09-21
申请人： Jin-Yuan Lee , Chue-San Yoo , Hsien Wei Chin
发明人： Jin-Yuan Lee , Chue-San Yoo , Hsien Wei Chin
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S148/055
摘要： An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.
摘要翻译：提出了在保险丝上的绝缘层的开口上形成保护层的改进的结构和方法。保护层防止污染物进入保险丝开口中暴露的绝缘层，而不会干扰保险丝的激光修整。形成穿过熔丝的层的开口形成垂直侧壁，其暴露部分绝缘层。在绝缘层，侧壁和熔断体上形成保护层，从而防止污染物扩散到暴露的绝缘层中。在熔断体上方的保护层中形成第二个开口，以允许激光束熔化下面的熔断体。

2. 发明授权

US5879966A Method of making an integrated circuit having an opening for a fuse 失效
标题翻译：制作具有保险丝开口的集成电路的方法
公开(公告)号：US5879966A
公开(公告)日：1999-03-09
申请号：US301536
申请日：1994-09-06
申请人： Jin-Yuan Lee , Chue-San Yoo , Hsien Wei Chin
发明人： Jin-Yuan Lee , Chue-San Yoo , Hsien Wei Chin
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S148/055
摘要： An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.
摘要翻译：提出了在保险丝上的绝缘层的开口上形成保护层的改进的结构和方法。保护层防止污染物进入保险丝开口中暴露的绝缘层，而不会干扰保险丝的激光修整。形成穿过熔丝的层的开口形成垂直侧壁，其暴露部分绝缘层。在绝缘层，侧壁和熔断体上形成保护层，从而防止污染物扩散到暴露的绝缘层中。在熔断体上方的保护层中形成第二个开口，以允许激光束熔化下面的熔断体。

3. 发明授权

US6071783A Pseudo silicon on insulator MOSFET device 有权
公开(公告)号：US6071783A
公开(公告)日：2000-06-06
申请号：US133353
申请日：1998-08-13
申请人： Mong-Song Liang , Jin-Yuan Lee , Chue-San Yoo
发明人： Mong-Song Liang , Jin-Yuan Lee , Chue-San Yoo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/417
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/41766
摘要： A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.

4. 发明授权

US5866451A Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic 失效
标题翻译：制造具有4t sram和混合模式电容器的半导体器件的方法
公开(公告)号：US5866451A
公开(公告)日：1999-02-02
申请号：US654498
申请日：1996-05-28
申请人： Chue-San Yoo , Mong-Song Liang , Jin-Yuan Lee
发明人： Chue-San Yoo , Mong-Song Liang , Jin-Yuan Lee
IPC分类号： H01L21/8239 , H01L21/8244 , H01L27/105 , H01L27/11 , H01L21/8242
CPC分类号： H01L27/11 , H01L27/105 , H01L27/1052 , H01L27/1112 , H01L27/1116
摘要： An integrated process for forming a 4T SRAM and a mixed-mode capacitor, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a bottom capacitor plate over a field oxide region in a capacitor region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates and capacitor bottom plate, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a top capacitor plate, and to form a load resistor for the SRAM.
摘要翻译：提供了在同一集成电路上形成具有逻辑的4T SRAM和混合模式电容器的集成过程。提供具有场隔离区域的半导体衬底，在场隔离区域之间具有栅极和栅极氧化物。多晶硅互连形成在场隔离区域的一部分上，仅在第一存储区域中，以及在电容器区域中的场氧化物区域上形成底部电容器板。有源区形成在衬底中，与每个栅极相邻。绝缘垫片形成在栅极，多晶硅互连和浮动栅极的侧壁上，并随后从互连中移除。在栅极和电容器底板上以及多晶硅互连和有源区上形成一层硅化钛。在半导体衬底上形成一个多晶硅氧化物。在多晶硅互连上的多晶硅氧化物中形成开口。第二层多晶硅沉积在衬底上。图案化第二层多晶硅以形成顶部电容器板，并形成用于SRAM的负载电阻器。

5. 发明授权

US5861673A Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations 失效
标题翻译：用于在多级集成电路中形成通孔的方法，用于多级金属化
公开(公告)号：US5861673A
公开(公告)日：1999-01-19
申请号：US787894
申请日：1997-01-23
申请人： Chue-San Yoo , Jin-Yuan Lee
发明人： Chue-San Yoo , Jin-Yuan Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L29/41
CPC分类号： H01L21/76838 , H01L23/5226 , H01L2924/0002
摘要： A process has been developed that allows reliable fabrication of vias, used for multi-level wiring purposes. The process features the use of a metallization structure, overlying a pillar structure in a specific area, resulting in a raised and extended metal surface, in areas of overlap. The raised and extended metal surface is used for subsequent via contact. Spin on glass processes are also employed to fill narrow spaces between metal structures.
摘要翻译：已经开发了一种允许可靠地制造用于多层布线目的的通孔的工艺。该方法的特征在于使用金属化结构，覆盖特定区域中的柱结构，导致在重叠区域中的凸起和延伸的金属表面。凸起和延伸的金属表面用于随后的通孔接触。旋转玻璃工艺也用于填充金属结构之间的狭窄空间。

6. 发明授权

US5712201A Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip 失效
标题翻译：在同一半导体芯片上集成逻辑和单级多晶硅DRAM器件的制造方法
公开(公告)号：US5712201A
公开(公告)日：1998-01-27
申请号：US660306
申请日：1996-06-07
申请人： Jin-Yuan Lee , Chue-San Yoo , Mong-Song Liang
发明人： Jin-Yuan Lee , Chue-San Yoo , Mong-Song Liang
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088
CPC分类号： H01L27/10844 , H01L21/823425 , H01L27/088
摘要： A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.
摘要翻译：已经开发了半导体制造工艺，其中DRAM和逻辑器件结构都集成在单个硅芯片上。该过程的特征是组合了两种器件类型的工艺步骤，同时对于高容量DRAM单元以及CMOS逻辑单元仅使用单层多晶硅。高容量DRAM单元由上覆多晶硅存储栅结构，薄介电层和下掺杂半导体区构成。

7. 发明授权

US5605853A Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells 失效
标题翻译：制造具有4个晶体管SRAM和浮动栅极存储单元的半导体器件的方法
公开(公告)号：US5605853A
公开(公告)日：1997-02-25
申请号：US654131
申请日：1996-05-28
申请人： Chue-San Yoo , Mong-Song Liang , Jin-Yuan Lee
发明人： Chue-San Yoo , Mong-Song Liang , Jin-Yuan Lee
IPC分类号： H01L27/105 , H01L27/11 , H01L21/8247 , H01L21/8244
CPC分类号： H01L27/1112 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/11546
摘要： An integrated process for forming a 4T SRAM and a floating gate memory, with logic, on the same integrated circuit, is provided. A semiconductor substrate is provided having field isolation regions, with a gate and gate oxide between the field isolation regions. Polysilicon interconnects are formed over a portion of the field isolation regions, only in a first memory region, and a floating gate over a field oxide region in a second memory region. Active regions are formed in the substrate, adjacent to each gate. Insulating spacers are formed on the sidewalls of the gates, polysilicon interconnects and the floating gate, and later removed from the interconnect. A layer of titanium silicide is formed over the gates, except over the floating gate in the second memory region, and also over the polysilicon interconnects and active regions. An interpoly oxide is formed over the semiconductor substrate. An opening is formed in the interpoly oxide over the polysilicon interconnect. A second layer of polysilicon is deposited over the substrate. The second layer of polysilicon is patterned to form a control gate over the floating gate, and to form a load resistor for the SRAM.
摘要翻译：提供了一种用于在同一集成电路上形成具有逻辑的4T SRAM和浮动栅极存储器的集成过程。提供具有场隔离区域的半导体衬底，在场隔离区域之间具有栅极和栅极氧化物。多晶硅互连形成在场隔离区域的一部分上，仅在第一存储区域中，以及位于第二存储区域中的场氧化物区域上的浮置栅极。有源区形成在衬底中，与每个栅极相邻。绝缘垫片形成在栅极，多晶硅互连和浮动栅极的侧壁上，并随后从互连中移除。在栅极上形成一层硅化钛，除了第二存储区域中的浮置栅极之外以及多晶硅互连和有源区域之外。在半导体衬底上形成一个多晶硅氧化物。在多晶硅互连上的多晶硅氧化物中形成开口。第二层多晶硅沉积在衬底上。图案化第二层多晶硅以在浮动栅极上形成控制栅极，并形成SRAM的负载电阻。

8. 发明授权

US5180689A Tapered opening sidewall with multi-step etching process 失效
标题翻译：锥形开口侧壁采用多步蚀刻工艺
公开(公告)号：US5180689A
公开(公告)日：1993-01-19
申请号：US757135
申请日：1991-09-10
申请人： Hsien-Tsung Liu , Jin-Yuan Lee , Jiann-Kwang Wang , Chue-San Yoo , Pei-Jan Wang
发明人： Hsien-Tsung Liu , Jin-Yuan Lee , Jiann-Kwang Wang , Chue-San Yoo , Pei-Jan Wang
IPC分类号： H01L21/768
CPC分类号： H01L21/76804
摘要： A method is described for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor. An integrated circuit structure is provided having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the said multilayer insulating layer having openings therein in the areas where the said openings are desired. The multilayer insulating layer is anisotropically etched through a first thickness to form a first opening using the resist masking layer as a mask. A second thickness portion of the multilayer insulating layer is isotropically etched to substantially uniformly enlarge and taper the first opening while using the unchanged resist layer. The remaining thickness of the multilayer insulating layer is anisotropically etched through to the semiconductor substrate to form the desirable tapered opening with a metal step coverage improvement over the state of the art between about 20 to 60%. Metal step coverage is defined as the ratio of thickness of the thinnest metal in the contact hole to the metal thickness on the horizontal area. The resist layer mask is removed.
摘要翻译：描述了一种用于制造具有约1微米或更小的特征尺寸的集成电路的锥形开口的方法，其将在适当的时候被冶金导体填充。提供了一种集成电路结构，其具有半导体衬底内的器件元件及其上的多层绝缘层。在需要所述开口的区域中，在其上具有开口的所述多层绝缘层上形成抗蚀剂掩模层。多层绝缘层通过第一厚度进行各向异性蚀刻，以形成使用抗蚀剂掩模层作为掩模的第一开口。多层绝缘层的第二厚度部分被各向同性地蚀刻，以在使用未改变的抗蚀剂层的同时大致均匀地放大和渐缩第一开口。将多层绝缘层的剩余厚度各向异性地蚀刻到半导体衬底上以形成期望的锥形开口，其中的现有技术的金属级覆盖改善在约20％至60％之间。金属台阶覆盖率定义为接触孔中最薄金属的厚度与水平面上的金属厚度之比。去除抗蚀剂层掩模。

9. 发明授权

US6093616A Method of manufacture of stacked gate MOS structure for multiple voltage power supply applications 失效
标题翻译：用于多电压电源应用的堆叠栅极MOS结构的制造方法
公开(公告)号：US6093616A
公开(公告)日：2000-07-25
申请号：US75366
申请日：1998-05-11
申请人： Mong-Song Liang , Jin-Yuan Lee , Chue-San Yoo
发明人： Mong-Song Liang , Jin-Yuan Lee , Chue-San Yoo
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/40
摘要： This method forms a capacitor structure on a semiconductor substrate for providing split voltages for semiconductor circuits by the following steps. Form an active area in the substrate serving as a lower capacitor plate for a bottom capacitor and then form a thin dielectric layer and field oxide regions on the substrate, and cover the dielectric layer with a capacitor plate over the active area to complete the bottom capacitor. Form a thick dielectric layer over the device and a via through the thick dielectric layer to the upper capacitor plate. Form a second lower plate for a top capacitor. Form an inter-layer dielectric layer over the second lower plate. Form an upper capacitor layer over the inter-layer dielectric layer to form a top capacitor with a different capacitance value from the bottom capacitor. The value of the capacitance can be varied by selection of the permittivity and/or thickness of the dielectric layer and by variation of the effective plate area of the top and bottom capacitors.
摘要翻译：该方法通过以下步骤在半导体基板上形成用于半导体电路的分压的电容器结构。在用作底部电容器的下电容器板的衬底中形成有源区，然后在衬底上形成薄的电介质层和场氧化物区域，并且在有源区域上用电容器板覆盖电介质层以完成底部电容器。在器件上形成厚电介质层，并通过厚电介质层通孔到上电容器板。形成顶部电容器的第二个下板。在第二下板上形成层间电介质层。在层间电介质层上形成上层电容层，形成与底层电容不同的电容值的顶层电容。可以通过选择介电层的介电常数和/或厚度以及顶部和底部电容器的有效平板面积的变化来改变电容的值。

10. 发明授权

US5900658A Logic and single level polysilicon DRAM devices fabricated on the same semiconductor chip 失效
标题翻译：在同一半导体芯片上制造的逻辑和单级多晶硅DRAM器件
公开(公告)号：US5900658A
公开(公告)日：1999-05-04
申请号：US950233
申请日：1997-10-14
申请人： Jin-Yuan Lee , Chue-San Yoo , Mong-Song Liang
发明人： Jin-Yuan Lee , Chue-San Yoo , Mong-Song Liang
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L7/01
CPC分类号： H01L27/10844 , H01L21/823425 , H01L27/088
摘要： A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.
摘要翻译：已经开发了半导体制造工艺，其中DRAM和逻辑器件结构都集成在单个硅芯片上。该过程的特征是组合了两种器件类型的工艺步骤，同时对于高容量DRAM单元以及CMOS逻辑单元仅使用单层多晶硅。高容量DRAM单元由上覆多晶硅存储栅结构，薄介电层和下掺杂半导体区构成。

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