专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06271125B1 Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure 有权
公开(公告)号：US06271125B1
公开(公告)日：2001-08-07
申请号：US09713799
申请日：2000-11-16
申请人： Chue-san Yoo , Chen-Jong Wang , Wen-Chuan Chiang
发明人： Chue-san Yoo , Chen-Jong Wang , Wen-Chuan Chiang
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/31116 , H01L21/76816 , H01L27/10855 , H01L27/10888 , H01L27/10897
摘要： A method for reducing the high aspect ratios, encountered when forming, and filling, narrow diameter contact holes, in thick insulator layers, has been developed, featuring a two step contact hole opening and filling procedure. First, lower narrow diameter contact holes are opened in lower levels of insulator layers, then filled with tungsten. After deposition of upper levels of insulator layers, upper narrow diameter contact holes are formed, exposing the tungsten filled, lower diameter contact holes. A second tungsten layer fills the upper, narrow diameter contact hole, resulting in a final narrow diameter contact hole, in thick insulator layers, formed with reduced aspect ratios, via use of the two contact hole openings, and the two tungsten fill procedures. In addition these procedures allow a damascene, tungsten bit line structure, to be formed in a dual shaped opening, in lower insulator layers.

2. 发明授权

US6033969A Method of forming a shallow trench isolation that has rounded and protected corners 失效
标题翻译：形成具有圆形和保护角的浅沟槽隔离的方法
公开(公告)号：US6033969A
公开(公告)日：2000-03-07
申请号：US721758
申请日：1996-09-30
申请人： Chue-San Yoo , R. Y. Lee , J. H. Tsai
发明人： Chue-San Yoo , R. Y. Lee , J. H. Tsai
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76224 , H01L21/76235
摘要： A method is provided for forming a shallow trench isolation that has rounded and protected corners by first forming a bird's beak field oxide layer prior to the trench-forming step such that a rounded and protected top corner and a rounded bottom corner of the trench can be formed. The rounded top and bottom corners of the shallow trench opening have a radius of at least 100 .ANG. and a trench depth of not more than 5000 .ANG.. The top corner of the trench opening is protected by the beak portion of the bird's beak against etching in a subsequent oxide dip process before gate formation.
摘要翻译：提供了一种用于形成具有圆形和保护角的浅沟槽隔离的方法，首先在沟槽形成步骤之前形成鸟喙场氧化物层，使得沟槽的圆形和受保护的顶角和圆角底角可以是形成。浅沟槽开口的圆形顶部和底部角部的半径至少为100安培，沟槽深度不超过5000安培。沟槽开口的顶角由鸟喙的喙部分保护，在栅极形成之前的随后的氧化物浸渍过程中被蚀刻。

3. 发明授权

US6017791A Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer 失效
标题翻译：用于形成低氧化温度的氧化氮化硅/氧化硅（no）层的多层氮化硅沉积方法
公开(公告)号：US6017791A
公开(公告)日：2000-01-25
申请号：US967655
申请日：1997-11-10
申请人： Chen-Jong Wang , Chue-San Yoo , Kuo-Hsien Cheng
发明人： Chen-Jong Wang , Chue-San Yoo , Kuo-Hsien Cheng
IPC分类号： H01L21/02 , H01L21/314 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/40 , H01L21/3145 , Y10S438/954
摘要： A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer. The silicon nitride/silicon oxide (NO) layer may be formed with optimized resistivity properties at a reduced thermal annealing temperature and/or a reduced thermal annealing exposure time in comparison with an otherwise equivalent silicon nitride/silicon oxide (NO) layer formed through thermal annealing a single silicon nitride layer of thickness equivalent to the thickness of the first silicon nitride layer plus the thickness of the second silicon nitride layer. When formed upon a silicon oxide dielectric layer in turn formed upon a first capacitor plate within a capacitor within an integrated circuit, there may be formed employing the silicon nitride/silicon oxide (NO) layer a silicon oxide/silicon nitride/silicon oxide (ONO) capacitive dielectric layer.
摘要翻译：在微电子制造中形成氮化硅/氧化硅（NO）层的方法以及其中形成有氮化硅/氧化硅（NO）层的微电子制造。首先提供了在微电子制造中使用的衬底。然后通过第一沉积方法在衬底上形成第一氮化硅层。然后通过第二沉积方法在第一氮化硅层上形成第二氮化硅层。最后，在氧化环境中，热处理第一氮化硅层和第二氮化硅层，由此形成氮化硅/氧化硅（NO）层。氮化硅/氧化硅（NO）层可以在降低的热退火温度和/或降低的热退火暴露时间的情况下形成具有优化的电阻率特性，与通过热形成的其它等效的氮化硅/氧化硅（NO）层相比较退火厚度等于第一氮化硅层厚度的单个氮化硅层加上第二氮化硅层的厚度。当形成在集成电路内的电容器内的第一电容器板上的氧化硅电介质层上形成时，可以形成采用氮化硅/氧化硅（NO）层的氧化硅/氮化硅/氧化硅（ONO ）电容电介质层。

4. 发明授权

US6015730A Integration of SAC and salicide processes by combining hard mask and poly definition 失效
标题翻译：通过组合硬掩模和聚合物定义来整合SAC和自杀化合物过程
公开(公告)号：US6015730A
公开(公告)日：2000-01-18
申请号：US34926
申请日：1998-03-05
申请人： Chen-Jong Wang , Jenn Ming Huang , Chue San Yoo
发明人： Chen-Jong Wang , Jenn Ming Huang , Chue San Yoo
IPC分类号： H01L21/02 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11526 , H01L21/76897 , H01L27/10873 , H01L27/11543 , H01L29/665 , H01L21/76895 , H01L28/60
摘要： A process and structure are described wherein logic and memory share the same chip. Contacts to the memory circuits are made using the SAC process, thus ensuring maximum density, while contacts to the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first depositing the various layers needed by the gate pedestals in both the logic and the memory areas and then forming the two sets of gate pedestals in separate steps. Gates located in the logic area are formed only from polysilicon while those located in the memory areas also have an overlay of tungsten silicide topped by a hard mask of silicon nitride. With the two sets of gates in place, source/drain regions are formed in the usual way. This includes growing of silicon nitride spacers on the vertical sides of the pedestals. The pedestals in the memory area are much longer than those in the logic area since they extend all the way to the top of the hard masks. The pedestals, on the memory side only, are given a protective coating of oxide (RPO). This allows the SALICIDE process to be selectively applied to only the logic side. Then, while the logic side is protected, the SAC process is applied to the memory side. This process is self-aligning. The long spacers define the contact holes and the hard masks allow oversize openings to be etched without the danger of shorting through to the pedestals.
摘要翻译：描述了其中逻辑和存储器共享相同芯片的过程和结构。与存储器电路的接触使用SAC工艺制成，从而确保了最大密度，同时使用SALICIDE工艺进行与逻辑电路的接触，从而确保了高性能。通过首先将逻辑和存储区域中的栅极基座所需的各种层淀积，然后在分开的步骤中形成两组栅极基座，将这两个工艺集成在单个芯片内。位于逻辑区域中的栅极仅由多晶硅形成，而位于存储区域中的栅极也具有由氮化硅硬掩模顶上的硅化钨覆盖层。通过两组门就位，源/漏区以常规方式形成。这包括在基座的垂直侧上生长氮化硅间隔物。存储区中的基座比逻辑区域中的基座长得多，因为它们一直延伸到硬掩模的顶部。仅在记忆方面的基座被赋予氧化物保护层（RPO）。这允许将SALICIDE过程选择性地仅应用于逻辑侧。然后，当逻辑侧被保护时，SAC进程被应用于存储器侧。这个过程是自调整的。长的间隔件限定接触孔，并且硬掩模允许蚀刻大尺寸的开口，而不会短路到基座的危险。

5. 发明授权

US5470779A Method of manufacture of SRAM with SIPOS resistor 失效
标题翻译：使用SIPOS电阻制造SRAM的方法
公开(公告)号：US5470779A
公开(公告)日：1995-11-28
申请号：US280219
申请日：1994-07-25
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112 , Y10S257/904
摘要： A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolyslicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.
摘要翻译：在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的方法包括在所述半导体衬底上形成多晶硅1层。多晶硅1层被图案化和蚀刻。在多晶硅1层上形成多层硅化物层，经图案化和蚀刻，形成穿过多晶硅层的开口，暴露多晶硅1层表面上的接触面积。 SIPOS层在通过开口与多晶硅1层接触的多晶硅层上形成电阻材料。在要形成在SIPOS层中的负载电阻器区域上形成负载电阻器掩模，并且将离子注入到不被负载电阻器掩模覆盖的SIPOS层的其余部分中，以将SIPOS层的其余部分从电阻器转换成互连结构与负载电阻器区域中的负载电阻器成一体。

6. 发明授权

US5411907A Capping free metal silicide integrated process 失效
标题翻译：无盖金属硅化物集成工艺
公开(公告)号：US5411907A
公开(公告)日：1995-05-02
申请号：US937735
申请日：1992-09-01
申请人： Chue-San Yoo , Jyh-Min Tsaur , Chong-Shi Chen , Pin-Nan Tseng
发明人： Chue-San Yoo , Jyh-Min Tsaur , Chong-Shi Chen , Pin-Nan Tseng
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/6659
摘要： A method is described for fabricating a lightly doped drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode continues by annealing the gate oxide, the polysilicon layer and the metal silicide layer using a furnace process at a temperature more than about 920.degree. C. and for a time of less than about 40 minutes. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The pattern of lightly doped regions is driven in while maintaining the low temperature silicon oxide over the metal silicide layer by annealing at a temperature of more than about 920.degree. C. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Heavily doped regions are formed. A passivation layer which includes a silicon oxide layer and a thicker dielectric layer is formed over the structures. The heavily doped regions are annealed to drivein the impurities at a temperature of more than about 920.degree. C. while maintaining said passivation layer over said metal silicide layer.
摘要翻译：描述了一种用于制造具有无剥离金属硅化物栅电极的轻掺杂漏极MOS FET集成电路器件的方法，其通过使用炉法在大于约920的温度下退火栅极氧化物，多晶硅层和金属硅化物层并且时间小于约40分钟。通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。低温二氧化硅层被覆盖在该结构的表面上。驱动轻掺杂区域的图案，同时通过在超过约920℃的温度下退火，在金属硅化物层上保持低温氧化硅的同时，蚀刻覆盖层以在每个侧壁上形成电介质间隔物结构的栅极电极结构和衬底的相邻部分之上，并从金属硅化物层的顶表面去除氧化硅层。形成重掺杂区域。在结构上形成包括氧化硅层和较厚电介质层的钝化层。重掺杂区域被退火以在大于约920℃的温度下驱动杂质，同时将所述钝化层保持在所述金属硅化物层上。

7. 发明授权

US06346729B1 Pseudo silicon on insulator MOSFET device 有权
标题翻译：伪硅绝缘体MOSFET器件
公开(公告)号：US06346729B1
公开(公告)日：2002-02-12
申请号：US09575445
申请日：2000-05-22
申请人： Mong-Song Liang , Jin-Yuan Lee , Chue-san Yoo
发明人： Mong-Song Liang , Jin-Yuan Lee , Chue-san Yoo
IPC分类号： H01L31119
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/41766
摘要： A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.
摘要翻译：已经开发了通过使用薄氧化硅层形成具有从半导体衬底隔离的重掺杂源/漏区的MOSFET器件的工艺。在形成轻掺杂的源极/漏极区之后，在绝缘体间隔物，栅极结构和绝缘体填充的浅沟槽区域之间的区域中，在半导体衬底中产生开口，导致轻掺杂的源极/漏极段，剩余在掩蔽绝缘体垫片下面。在暴露的硅表面上形成薄的氧化硅层之后，在开口中，执行硅沉积和回蚀程序，将开口部分地再填充到仍允许薄氧化硅层暴露在侧面的深度的轻掺杂源极/漏极段。在去除薄氧化硅层的暴露部分之后，并且在另一硅层沉积和蚀回之后，完全填充开口，在存在于开口中的硅层中形成重掺杂的源极/漏极区。

8. 发明授权

US5943569A Method for making improved capacitors on dynamic random access memory having increased capacitance, longer refresh times, and improved yields 失效
标题翻译：用于在动态随机存取存储器中制造改进的电容器的方法，其具有增加的电容，更长的刷新次数和提高的
公开(公告)号：US5943569A
公开(公告)日：1999-08-24
申请号：US880854
申请日：1997-06-23
申请人： Cheng-Yeh Shih , Yuan-Chang Huang , Chue-San Yoo , Wen-Chan Lin
发明人： Cheng-Yeh Shih , Yuan-Chang Huang , Chue-San Yoo , Wen-Chan Lin
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L27/10852 , H01L28/60
摘要： A method for making improved capacitor bottom electrodes (capacitor nodes) having longer refresh cycle times and increased capacitance for DRAM cells has been achieved. The method involves using a polysilicon high-temperature film (HTF) instead of the conventional doped polysilicon to form the node capacitors. After forming the DRAM pass transistors (FETs) and depositing an insulating layer, node contact openings are etched in the insulator to the drain of the FET. The capacitor bottom electrodes are formed by depositing a polysilicon HTF at a temperature of at least 650.degree. C. using a reactant gas mixture of H.sub.2 /SiH.sub.4 /PH.sub.3, which results in a longer refresh cycle time and increased capacitance. This results in a significantly improved final die yield. After forming an interelectrode dielectric layer on the bottom electrodes, another doped polysilicon layer is deposited to form the top electrodes to complete the DRAM cells.
摘要翻译：已经实现了具有更长的刷新周期时间和DRAM单元的增加的电容的改进的电容器底部电极（电容器节点）的方法。该方法包括使用多晶硅高温膜（HTF）代替常规的掺杂多晶硅以形成节点电容器。在形成DRAM通过晶体管（FET）和沉积绝缘层之后，将节点接触开口在绝缘体中蚀刻到FET的漏极。通过使用H 2 / SiH 4 / PH 3的反应气体混合物在至少650℃的温度下沉积多晶硅HTF来形成电容器底部电极，这导致更长的刷新周期时间和增加的电容。这导致最终模具产量显着提高。在底部电极上形成电极间电介质层之后，沉积另一个掺杂多晶硅层以形成顶部电极以完成DRAM单元。

9. 发明授权

US5670423A Method for using disposable hard mask for gate critical dimension control 失效
标题翻译：使用一次性硬掩模进行浇口关键尺寸控制的方法
公开(公告)号：US5670423A
公开(公告)日：1997-09-23
申请号：US663431
申请日：1996-06-13
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/28123 , H01L21/32139 , Y10S438/95 , Y10S438/952
摘要： A new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A layer of polysilicon is deposited over the uneven surface of the substrate. The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography. A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light. The semiconductor layer is covered with a uniform thickness layer of photoresist. The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer. The semiconductor layer, the spin-on-glass layer, and the polysilicon layer not covered by the photoresist mask are anisotropically etched away to form polysilicon gate electrodes and interconnection lines. The photoresist mask, the hard mask, and the spin-on-glass layer are removed to complete the formation of polysilicon gate electrodes and interconnection lines having uniform critical dimension in the fabrication of an integrated circuit.
摘要翻译：描述了通过使用一次性硬掩模来控制多晶硅的临界尺寸宽度的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在衬底的不平坦表面上沉积多晶硅层。多晶硅层被旋涂玻璃层覆盖，其中旋涂玻璃材料平坦化底层地形的表面。半导体层沉积在平坦化层的表面上以用作硬掩模，其中半导体层对于光化光是不透明的。半导体层被均匀厚度的光致抗蚀剂层覆盖。光致抗蚀剂层暴露于光化学光，其中半导体层防止光化反射光从其表面。显影和图案化光致抗蚀剂层以形成多晶硅层所需的光刻胶掩模。将不被光致抗蚀剂掩模覆盖的半导体层，旋涂玻璃层和多晶硅层各向异性地蚀刻掉以形成多晶硅栅电极和互连线。去除光致抗蚀剂掩模，硬掩模和旋涂玻璃层，以在集成电路的制造中完成多晶硅栅电极和具有均匀临界尺寸的互连线的形成。

10. 发明授权

US5573980A Method of forming salicided self-aligned contact for SRAM cells 失效
标题翻译：形成SRAM单元的水银自对准接触的方法
公开(公告)号：US5573980A
公开(公告)日：1996-11-12
申请号：US583917
申请日：1996-04-22
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/285 , H01L21/28
CPC分类号： H01L21/28518
摘要： This invention provides a method of forming very low resistance self-aligned silicide contacts to devices formed in a silicon integrated circuit substrate while avoiding the formation of stringers or stray silicide conductor paths. The method uses a thin layer of polysilicon which is patterned so as to only cover the contact region of the device being contacted. A layer of metal such as titanium is then deposited and the silicide is formed using rapid thermal annealing. The unreacted metal is then etched away. The primary application is to form a low resistance V.sub.ss plate for adjacent pull down transistors in SRAM cells but can be used in any device requiring a low resistance contact to silicon.
摘要翻译：本发明提供了一种形成非常低电阻的自对准硅化物触点到形成在硅集成电路衬底中的器件的方法，同时避免形成桁条或杂散硅化物导体路径。该方法使用图案化的薄层多晶硅，以仅覆盖被接触的器件的接触区域。然后沉积诸如钛的金属层，并且使用快速热退火形成硅化物。然后将未反应的金属蚀刻掉。主要的应用是形成用于SRAM单元中的相邻下拉晶体管的低电阻Vss板，但可用于需要与硅电阻低的触点的任何器件中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式