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    • 6. 发明授权
    • Add compare select circuit and method implementing a viterbi algorithm
    • 添加比较选择电路和实现维特比算法的方法
    • US6148431A
    • 2000-11-14
    • US49158
    • 1998-03-26
    • Inkyu LeeJeffrey Lee Sonntag
    • Inkyu LeeJeffrey Lee Sonntag
    • G06F11/10H03M13/23H03M13/41H03M13/03
    • H03M13/6502H03M13/3961H03M13/4107H03M13/4115H03M13/413
    • A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.
    • 采用维特比算法的检测器系统包括一种装置和方法,该装置和方法构建用于相对于观察到的信道输出样本序列确定最可能的接收符号序列的双状态网格结构。 在双状态网格中,识别出具有等效分支度量值的状态对,其在路径选择期间也具有相同的决定,从而允许这些状态对共享先前状态度量的比较操作。 因此,为了计算更新或当前状态度量值,加法,比较和选择(ACS)电路可以仅比较先前的状态度量值以确定两个状态之间的转换的最小值,同时将每个先前的状态度量值与其 相应的分支度量以提供更新或当前状态度量值。
    • 10. 发明授权
    • Block processing in a maximum a posteriori processor for reduced power consumption
    • 在最大后验处理器中进行块处理,以降低功耗
    • US07353450B2
    • 2008-04-01
    • US10054687
    • 2002-01-22
    • Thaddeus J. GabaraInkyu LeeMarissa L. Lopez-VallejoSyed Mujtaba
    • Thaddeus J. GabaraInkyu LeeMarissa L. Lopez-VallejoSyed Mujtaba
    • H03M13/03
    • H04L1/0055H03M13/3905H03M13/395H03M13/3972H04L1/0053
    • A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k−N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm. During the update process, the read/write operation for an implementation transfers N words of length N for each update operation, but the frequency (and hence, number) of update operations is reduced by a factor of N. Such voltage scaling and multiple word memory read/write may provide reduced power consumption for a given implementation of MAP processor in, for example, a DSP.
    • 最大后验(MAP)处理器采用用于MAP算法的块处理技术来提供允许给定电路实现的多个字存储器读/写处理和电压缩放的并行架构。 块处理技术形成具有修改的分支输入的状态的合并网格以提供并行结构。 当块处理发生时,网格可以被修改以显示从时间k-N处的最旧状态到时间k的当前状态的转换。 对于合并的网格,状态数量保持不变,但是每个状态都接收两个输入转换,而不是两个输入转换。 与合并网格中的转换相关联的分支度量是累积的,并且被MAP算法用于前向和后向概率的更新过程。 在更新过程中,对于每个更新操作,实现的读/写操作传送N个长度为N的字,但更新操作的频率(因此,数量)减少了N倍。这种电压缩放和多个字 存储器读/写可以为例如DSP中的MAP处理器的给定实现提供降低的功耗。