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1. 发明授权

US06573168B2 Methods for forming conductive contact body for integrated circuits using dummy dielectric layer 有权
公开(公告)号：US06573168B2
公开(公告)日：2003-06-03
申请号：US09866323
申请日：2001-05-25
申请人： Ji-soo Kim , Chang-woong Chu , Dong-hyun Kim , Yong-chul Oh , Hyoung-joon Kim , Byeong-yun Nam , Kyung-won Park , Sang-hyeop Lee
发明人： Ji-soo Kim , Chang-woong Chu , Dong-hyun Kim , Yong-chul Oh , Hyoung-joon Kim , Byeong-yun Nam , Kyung-won Park , Sang-hyeop Lee
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76801 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

2. 发明授权

US06429107B2 Method for forming conductive contact of semiconductor device 有权
标题翻译：用于形成半导体器件的导电接触的方法
公开(公告)号：US06429107B2
公开(公告)日：2002-08-06
申请号：US09839855
申请日：2001-04-20
申请人： Hyoung-joon Kim , Byeong-yun Nam , Kyung-won Park
发明人： Hyoung-joon Kim , Byeong-yun Nam , Kyung-won Park
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76801
摘要： A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.
摘要翻译：提供一种用于形成半导体器件的导电接触的方法。根据本发明的一个方面，在半导体衬底上形成有用于填充虚拟开口的具有比虚拟电介质层低的蚀刻速率的虚拟开口和介电层图案的虚拟介电层图案。选择性地去除使用电介质层图案作为蚀刻掩模的虚拟介电层图案，以及用于使虚设电介质层图案所在的部分露出半导体基板的接触开口。

3. 发明授权

US07009257B2 Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby 有权
公开(公告)号：US07009257B2
公开(公告)日：2006-03-07
申请号：US10741751
申请日：2003-12-19
申请人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
发明人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
IPC分类号： H01L29/72
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823475
摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

4. 发明授权

US06689654B2 Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad 有权
标题翻译：制造在基板和接触垫之间具有降低的接触电阻同时保持基板和接触垫的分离的集成电路器件的方法
公开(公告)号：US06689654B2
公开(公告)日：2004-02-10
申请号：US10038967
申请日：2002-01-04
申请人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
发明人： Young-pil Kim , Beom-jun Jin , Hyoung-joon Kim , Byeong-yun Nam
IPC分类号： H01L218238
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76895 , H01L21/823425 , H01L21/823475
摘要： An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.
摘要翻译：集成电路器件包括其中形成有源极区和漏极区的衬底。在源极区域和漏极区域之间的衬底上设置栅极图案。下焊盘层设置在源极区域和/或漏极区域上并且包括与衬底相同的晶体结构。导电层设置在下焊盘层上，使得导电层的至少一部分设置在下焊盘层和栅极图案之间。绝缘层设置在栅极图案与下焊盘层和导电层之间以及导电层和基板之间。

5. 发明授权

US06885052B2 Semiconductor memory device having self-aligned contacts and method of fabricating the same 失效
标题翻译：具有自对准触点的半导体存储器件及其制造方法
公开(公告)号：US06885052B2
公开(公告)日：2005-04-26
申请号：US09790240
申请日：2001-02-21
申请人： Tae-hyuk Ahn , Myeong-cheol Kim , Jung-hyeon Lee , Byeong-yun Nam , Gyung-jin Min
发明人： Tae-hyuk Ahn , Myeong-cheol Kim , Jung-hyeon Lee , Byeong-yun Nam , Gyung-jin Min
IPC分类号： H01L27/10 , H01L21/60 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10814 , H01L27/10888
摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.
摘要翻译：一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准与第二和第一间隔物。

6. 发明授权

US6004882A Method for etching Pt film of semiconductor device 失效
标题翻译：蚀刻半导体器件的Pt膜的方法
公开(公告)号：US6004882A
公开(公告)日：1999-12-21
申请号：US16022
申请日：1998-01-30
申请人： Hyoun-woo Kim , Byeong-yun Nam , Byong-sun Ju , Won-jong Yoo
发明人： Hyoun-woo Kim , Byeong-yun Nam , Byong-sun Ju , Won-jong Yoo
IPC分类号： C23F4/00 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/32136 , H01L21/28512
摘要： A method for etching a platinum (Pt) layer of a semiconductor device is provided which improves the etching slope of a sidewall of the platinum layer used as a storage node of the semiconductor device. The semiconductor device consists of a semiconductor substrate including a bottom layer on which various other layers are formed. Specifically, according to this invention, a Pt layer is formed on a bottom layer of a semiconductor substrate. An adhesive layer is then formed on the Pt layer while a mask layer is formed on the adhesive layer. After formation of the various layers, the mask layer and adhesive layer are patterned using an etching process to form a mask pattern and an adhesive layer mask pattern, respectively. The semiconductor substrate is then heated and an etching process is performned on the Pt layer using the mask pattern and the adhesive layer mask pattern to form etching slope sidewalls of the Pt layer having etching slopes close to vertical. Accordingly, the Pt electrodes of the semiconductor device of the present invention have a finer pattern than those of the prior art. Finally, overetching is done to remove the mask pattern.
摘要翻译：提供一种用于蚀刻半导体器件的铂（Pt）层的方法，其改善了用作半导体器件的存储节点的铂层的侧壁的蚀刻斜率。半导体器件由包括其上形成有各种其它层的底层的半导体衬底组成。具体地，根据本发明，在半导体衬底的底层上形成Pt层。然后在Pt层上形成粘合剂层，同时在粘合剂层上形成掩模层。在形成各层之后，使用蚀刻工艺对掩模层和粘合剂层进行图案化以分别形成掩模图案和粘合剂层掩模图案。然后加热半导体衬底并使用掩模图案和粘合剂层掩模图案在Pt层上进行蚀刻处理，以形成具有接近垂直的蚀刻斜率的Pt层的蚀刻斜面侧壁。因此，本发明的半导体器件的Pt电极具有比现有技术更精细的图案。最后，进行过蚀刻以去除掩模图案。

7. 发明授权

US06664585B2 Semiconductor memory device having multilayered storage node contact plug and method for fabricating the same 失效
公开(公告)号：US06664585B2
公开(公告)日：2003-12-16
申请号：US10012563
申请日：2001-12-12
申请人： Beom-jun Jin , Byeong-yun Nam
发明人： Beom-jun Jin , Byeong-yun Nam
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L27/10885 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

8. 发明授权

US06187686B1 Methods for forming patterned platinum layers using masking layers including titanium and related structures 有权
标题翻译：使用包括钛的掩模层形成图案化铂层的方法
公开(公告)号：US06187686B1
公开(公告)日：2001-02-13
申请号：US09325171
申请日：1999-06-03
申请人： Hwa-sook Shin , Byeong-yun Nam
发明人： Hwa-sook Shin , Byeong-yun Nam
IPC分类号： H01L2144
CPC分类号： C23F1/02 , C23F4/00 , H01L21/0332 , H01L21/28061 , H01L21/28123 , H01L21/32139 , H01L29/4941
摘要： A method for forming a patterned platinum layer on a microelectronic substrate includes the steps of forming a platinum layer on the microelectronic substrate, and forming a mask layer on the platinum layer. In particular, the mask layer defines exposed portions of the platinum layer, and the mask layer comprises a mask material including titanium. The exposed portions of the platinum layer are then selectively removed to form the patterned platinum layer. Related structures are also disclosed.
摘要翻译：在微电子衬底上形成图案化铂层的方法包括在微电子衬底上形成铂层并在铂层上形成掩模层的步骤。具体地，掩模层限定铂层的曝光部分，掩模层包括包含钛的掩模材料。然后选择性地去除铂层的暴露部分以形成图案化的铂层。还公开了相关结构。

9. 发明授权

US6054391A Method for etching a platinum layer in a semiconductor device 失效
标题翻译：在半导体器件中蚀刻铂层的方法
公开(公告)号：US6054391A
公开(公告)日：2000-04-25
申请号：US138655
申请日：1998-08-24
申请人： Byeong-yun Nam , Byong-sun Ju
发明人： Byeong-yun Nam , Byong-sun Ju
IPC分类号： C23F4/00 , H01L21/02 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/02071 , H01L21/32136
摘要： A method of etching a platinum (Pt) layer of a semiconductor device includes the steps of forming a platinum layer on a semiconductor substrate, and forming a mask layer on the platinum layer. A photoresist pattern is formed on the mask layer and a mask pattern is formed by plasma-etching using the photoresist pattern as a mask. A platinum pattern is formed by plasma-etching using the photoresist pattern and the mask pattern as a mask. A platinum etching by-product is formed on the sidewalls of the photoresist pattern. The platinum layer is plasma-etched using Ar, Ar/Cl.sub.2 or Ar/HBr gas. The photoresist pattern is removed and then the platinum etching by-product and the mask pattern are removed by plasma etching. The platinum etching by-product is plasma-etched using Cl.sub.2 /O.sub.2 or HBr/O.sub.2 gas. The platinum pattern may be formed in the same etch chamber through multiple steps, and the platinum layer is etched using Ar, Ar/Cl.sub.2 or Ar/HBr, to thereby increase the etch rate and obtain a platinum pattern having a high etch slope.
摘要翻译：蚀刻半导体器件的铂（Pt）层的方法包括在半导体衬底上形成铂层并在铂层上形成掩模层的步骤。在掩模层上形成光致抗蚀剂图案，并且通过使用光致抗蚀剂图案作为掩模的等离子体蚀刻形成掩模图案。通过使用光致抗蚀剂图案和掩模图案作为掩模的等离子体蚀刻形成铂图案。在光致抗蚀剂图案的侧壁上形成铂蚀刻副产物。使用Ar，Ar / Cl2或Ar / HBr气体等离子体蚀刻铂层。去除光致抗蚀剂图案，然后通过等离子体蚀刻除去铂蚀刻副产物和掩模图案。铂蚀刻副产物使用Cl2 / O2或HBr / O2气体进行等离子体蚀刻。铂图案可以通过多个步骤在相同的蚀刻室中形成，并且使用Ar，Ar / Cl2或Ar / HBr蚀刻铂层，从而增加蚀刻速率并获得具有高蚀刻斜率的铂图案。

10. 发明授权

US07132708B2 Semiconductor memory device having self-aligned contacts and method of fabricating the same 失效
标题翻译：具有自对准触点的半导体存储器件及其制造方法
公开(公告)号：US07132708B2
公开(公告)日：2006-11-07
申请号：US11054593
申请日：2005-02-09
申请人： Tae-hyuk Ahn , Myeong-cheol Kim , Jung-hyeon Lee , Byeong-yun Nam , Gyung-jin Min
发明人： Tae-hyuk Ahn , Myeong-cheol Kim , Jung-hyeon Lee , Byeong-yun Nam , Gyung-jin Min
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10814 , H01L27/10888
摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.
摘要翻译：一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准与第二和第一间隔物。

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