专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06525737B1 Graphics processor with pipeline state storage and retrieval 有权
标题翻译：具有流水线状态存储和检索的图形处理器
公开(公告)号：US06525737B1
公开(公告)日：2003-02-25
申请号：US09378439
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元从多边形存储器接收输入并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

2. 发明授权

US07808503B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07808503B2
公开(公告)日：2010-10-05
申请号：US11613093
申请日：2006-12-19
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Yo , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/00 , G06T15/10
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

3. 发明授权

US06717576B1 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US06717576B1
公开(公告)日：2004-04-06
申请号：US09377503
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1500
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

4. 发明授权

US07167181B2 Deferred shading graphics pipeline processor having advanced features 有权
标题翻译：具有高级功能的延迟着色图形流水线处理器
公开(公告)号：US07167181B2
公开(公告)日：2007-01-23
申请号：US10458493
申请日：2003-06-09
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , Joseph P. Bratt , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Zhaoyu Gong , Thomas Y. Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew N. Papakipos , Jason R. Redgrave , Sushma S. Trivedi , Nathan D. Tuck , Shun Wai Go , Lindy Fung , Tuan D. Nguyen , Joseph P. Grass , Bo Hong , Abraham Mammen , Abbas Rashid , Albert Suan-Wei Tsay
IPC分类号： G06T1/20 , G06T15/40 , G09G5/00
CPC分类号： G06T15/30 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/20 , G06T15/405 , G06T15/50 , G06T15/83
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺的帧缓冲器和多个阶段隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

5. 发明授权

US06693639B2 Graphics processor with pipeline state storage and retrieval 有权
标题翻译：具有流水线状态存储和检索的图形处理器
公开(公告)号：US06693639B2
公开(公告)日：2004-02-17
申请号：US10290414
申请日：2002-11-07
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Shun Wai Go , Sushma S. Trivedi , Richard E. Hessel , Joseph P. Bratt
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
摘要翻译：延迟图形流水线处理器，包括与多边形单元相关联的模式提取单元和多边形存储器。模式提取单元从几何单元接收数据流，并将数据流分离成顶点数据，并将非顶点数据发送到多边形存储器进行存储。模式注入单元接收来自多边形存储器的输入，并将模式信息传送到一个或多个其他处理单元。模式注入单元保持识别已经缓存的信息的状态信息，并且不发送已经被缓存的信息，从而减少通信带宽。

6. 发明授权

US06577317B1 Apparatus and method for geometry operations in a 3D-graphics pipeline 有权
标题翻译： 3D图形流水线中几何运算的装置和方法
公开(公告)号：US06577317B1
公开(公告)日：2003-06-10
申请号：US09379144
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Jack Benkual , Vaughn T. Arnold , Tuan D. Nguyen , Richard E. Hessel , Stephen L. Dodgen , Shun Wai Go
发明人： Jerome F. Duluk, Jr. , Jack Benkual , Vaughn T. Arnold , Tuan D. Nguyen , Richard E. Hessel , Stephen L. Dodgen , Shun Wai Go
IPC分类号： G06T120
CPC分类号： G06T15/20 , G06T15/005 , G06T15/30 , G06T15/50
摘要： An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline including a block for performing transformations. In one embodiment, the block for performing transformations includes a co-extensive logical and first physical stages, as well as a second physical stage including multiple logical stages. The second physical stage includes multiple logical stages that interleave their execution.
摘要翻译：用于渲染3D图形图像的装置和方法优选地包括用于从图形应用程序接收命令的端口，用于将呈现的图像发送到显示器的输出和耦合到端口和输出的几何运算流水线，几何形状操作流程包括用于执行转换的块。在一个实施例中，用于执行变换的块包括共同扩展的逻辑和第一物理级，以及包括多个逻辑级的第二物理级。第二个物理阶段包括交错执行的多个逻辑阶段。

7. 发明授权

US08493482B2 Dual image sensor image processing system and method 有权
标题翻译：双图像传感器图像处理系统及方法
公开(公告)号：US08493482B2
公开(公告)日：2013-07-23
申请号：US12858922
申请日：2010-08-18
申请人： Guy Cote , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
发明人： Guy Cote , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
IPC分类号： H04N3/14 , H04N5/335 , H01L31/062
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译：提供了用于处理使用数字图像传感器获取的图像数据的各种技术。根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

8. 发明申请

US20120044372A1 DUAL IMAGE SENSOR IMAGE PROCESSING SYSTEM AND METHOD 有权
标题翻译：双图像传感器图像处理系统和方法
公开(公告)号：US20120044372A1
公开(公告)日：2012-02-23
申请号：US12858922
申请日：2010-08-18
申请人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
发明人： Guy Côté , Jeffrey E. Frederiksen , Joseph P. Bratt , Shun Wai Go , Timothy J. Millet
IPC分类号： H04N5/225 , H04N5/228
CPC分类号： H04N5/232 , H04N5/2258 , H04N5/23245
摘要： Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.
摘要翻译：提供了用于处理使用数字图像传感器获取的图像数据的各种技术。根据本公开的方面，一种这样的技术可以涉及在支持多个图像传感器的系统中对图像数据的处理。在一个实施例中，图像处理系统可以包括被配置为确定设备是以单个传感器模式（一个有源传感器）或双传感器模式（两个有源传感器）操作的控制电路。当在单传感器模式下操作时，数据可以从有源传感器的传感器接口直接提供给前端像素处理单元。当以双传感器模式操作时，来自第一和第二传感器的图像帧以交错的方式提供给前端像素处理单元。例如，在一个实施例中，来自第一和第二传感器的图像帧被写入存储器，然后以交错的方式读出到前端像素处理单元。

9. 发明授权

US08489376B2 Controller and fabric performance testing 失效
标题翻译：控制器和面料性能测试
公开(公告)号：US08489376B2
公开(公告)日：2013-07-16
申请号：US12860668
申请日：2010-08-20
申请人： Marc A. Schaub , Shun Wai Go , Sukalpa Biswas , Timothy J. Millet
发明人： Marc A. Schaub , Shun Wai Go , Sukalpa Biswas , Timothy J. Millet
IPC分类号： G06F17/50 , G06F13/00
CPC分类号： G06F17/5022
摘要： In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.
摘要翻译：在一个实施例中，可以使用控制器的寄存器传送级（RTL）表示（或其他周期精确表示）以及到控制器的通信结构中的电路来创建模型。请求源可以被交易者代替，交易者可以生成事务来测试结构和控制器的性能。因此，在该实施例中，仅需要控制器和结构电路的设计来建模性能。在一个实施例中，至少一些交易者可以是尝试模拟相应请求源的操作的行为交易者。在一些实施例中，其他交易者可以是统计分布。在一个实施例中，事务处理器可以包括交易发生器（例如行为或统计）和协议转换器，其被配置为在交易者连接到该结构的点处将生成的交易转换为使用中的通信协议。

10. 发明授权

US07240141B2 Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an I/O bus of a system-on-a-chip processor 有权
标题翻译：针对片上系统处理器的I / O总线的可编程虚拟间通道和虚拟通道指令发布规则
公开(公告)号：US07240141B2
公开(公告)日：2007-07-03
申请号：US10821397
申请日：2004-04-09
申请人： Chun Hung Ning , Laurent Rene Moll , Kwong-Tak Chui , Shun Wai Go , Piyush Shashikant Jamkhandi
发明人： Chun Hung Ning , Laurent Rene Moll , Kwong-Tak Chui , Shun Wai Go , Piyush Shashikant Jamkhandi
IPC分类号： G06F13/366
CPC分类号： G06F13/4031
摘要： A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format. An ordering rules logic module is operably connected to the first transaction conversion module and is further operable to control issuing of transactions in accordance with a dependency relationship between the individual transactions. The ordering rules logic module generates validated transactions that are provided to a second conversion transaction module which is operably connected to the second bus. The ordering rules logic module of the present invention is fully programmable and, therefore, does not need to be redesigned when the data processing system is adapted to operate on a new bus system.
摘要翻译：一种方法和装置，用于编程驻留在各种虚拟信道之间的指令的指令发布规则，以及用于片上系统处理器的I / O总线接口的相同虚拟通道。在本发明的方法和装置中，虚拟内信道依赖性和虚拟间信道依赖性都是完全可编程的，从而提供了优于现有技术I / O接口的显着优点。本发明的方法和装置广泛地包括用于管理第一总线和第二总线之间的数据交易的系统。第一交易转换模块可操作地连接到第一总线，并且可操作以从第一总线接收交易和第一格式，并将这些交易转换成内部格式。排序规则逻辑模块可操作地连接到第一交易转换模块，并且还可操作以根据各个交易之间的依赖关系来控制交易的发行。排序规则逻辑模块产生被提供给可操作地连接到第二总线的第二转换事务模块的验证事务。本发明的排序规则逻辑模块是完全可编程的，因此，当数据处理系统适于在新总线系统上操作时，不需要重新设计。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式