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1. 发明授权

US08122400B2 Logic difference synthesis 有权
标题翻译：逻辑差分合成
公开(公告)号：US08122400B2
公开(公告)日：2012-02-21
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

2. 发明申请

US20110004857A1 LOGIC DIFFERENCE SYNTHESIS 有权
标题翻译：逻辑差异综合
公开(公告)号：US20110004857A1
公开(公告)日：2011-01-06
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

3. 发明授权

US08365114B2 Logic modification synthesis 有权
标题翻译：逻辑修改综合
公开(公告)号：US08365114B2
公开(公告)日：2013-01-29
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.
摘要翻译：正在识别两个电路，一个原始和一个修改的电路，原始电路具有第一逻辑，并且该修改的电路具有第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化。在原始电路中检测到等效线，使得第一和第二逻辑等效于从电路输入到等价线。至少一个变化点位于与等价线相邻的逻辑门之间。如果可观察性条件得到满足，则可以接受更改点。可观察性条件在布尔满足度（SAT）公式中进行检查。通过使用SAT和布尔方程求解技术，使得第一逻辑变为等同于第二逻辑的方式，导出用于验证的变化点的替代逻辑。

4. 发明申请

US20120054699A1 CONVERGED LARGE BLOCK AND STRUCTURED SYNTHESIS FOR HIGH PERFORMANCE MICROPROCESSOR DESIGNS 有权
标题翻译：用于高性能微处理器设计的大块和结构化合成
公开(公告)号：US20120054699A1
公开(公告)日：2012-03-01
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

5. 发明授权

US08271920B2 Converged large block and structured synthesis for high performance microprocessor designs 有权
标题翻译：用于高性能微处理器设计的融合大块和结构化合成
公开(公告)号：US08271920B2
公开(公告)日：2012-09-18
申请号：US12868086
申请日：2010-08-25
申请人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Victor N. Kravets , Smita Krishnaswamy , Dorothy Kucar , Jagannathan Narasimhan , Ruchir Puri , Haifeng Qian , Haoxing Ren , Chin Ngai Sze , Louise H. Trevillyan , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
摘要翻译：示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成，对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

6. 发明申请

US20120054698A1 LOGIC MODIFICATION SYNTHESIS 有权
标题翻译：逻辑修改合成
公开(公告)号：US20120054698A1
公开(公告)日：2012-03-01
申请号：US12862838
申请日：2010-08-25
申请人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
发明人： Eli Arbel , David Geiger , Victor Kravets , Smita Krishnaswamy , Ruchir Puri , Haoxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer-executed method is disclosed which recognizes two circuits, an original and a modified circuit, with the original circuit having a first logic and the modified circuit having a second logic. The second logic is obtained by converting a modified specification into a preliminary gate-level form. The second logic contains at least one desired logic change relative to the first logic in order to realize the modified specification. The method includes detecting an equivalence line in the original circuit, such that the first and second logic are equivalent from the circuit inputs to the equivalence line, and finding at least one point of change amongst the logic gates that are neighboring the equivalence line. Next, accepting the points of change as verified point of change if an observability condition is fulfilled, which means that for every input vector for which an output of the original and modified circuits differ, at least one logic value of the points of change propagate to that output of the original circuit. This observability condition is checked within a Boolean Satisfiability (SAT) formulation. The method also includes deriving a substitute logic for the verified points of change, using SAT techniques, and Boolean equation solving techniques which solve for a change function at each point of change, in such manner that the first logic in the original circuit becomes equivalent to the second logic, and thereby implements the changed specification.
摘要翻译：公开了一种计算机执行方法，其识别具有第一逻辑的原始电路的两个电路，原始电路和修改的电路，并且修改的电路具有第二逻辑。通过将修改的规范转换成初级门级形式来获得第二逻辑。第二逻辑包含相对于第一逻辑的至少一个期望的逻辑变化，以便实现修改的规范。该方法包括检测原始电路中的等效线，使得第一和第二逻辑等效于从等效线路的电路输入，并找到与等价线相邻的逻辑门之间的至少一个变化点。接下来，如果满足可观察性条件，则将变化点接受为经验证的变化点，这意味着对于原始和修正电路的输出不同的每个输入向量，改变点的至少一个逻辑值传播到原始电路的输出。在布尔满足度（SAT）公式中检查此可观察性条件。该方法还包括使用SAT技术，以及在每个变化点解决变化函数的布尔方程求解技术，以使得原始电路中的第一逻辑等同于第二个逻辑，从而实现改变的规范。

7. 发明授权

US08756541B2 Relative ordering circuit synthesis 有权
标题翻译：相对排序电路综合
公开(公告)号：US08756541B2
公开(公告)日：2014-06-17
申请号：US13431368
申请日：2012-03-27
申请人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
发明人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.
摘要翻译：本文提供了相对排序电路合成的系统和方法。一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。本文还描述了其它实施例和方面。

8. 发明授权

US08566761B2 Network flow based datapath bit slicing 失效
标题翻译：基于网络流的数据路径位分片
公开(公告)号：US08566761B2
公开(公告)日：2013-10-22
申请号：US13301107
申请日：2011-11-21
申请人： Hua Xiang , Minsik Cho , Haoxing Ren , Matthew M Ziegler , Ruchir Puri
发明人： Hua Xiang , Minsik Cho , Haoxing Ren , Matthew M Ziegler , Ruchir Puri
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.
摘要翻译：本公开涉及一种用于确定数据路径位片的基于计算机的方法和装置。在输入向量和输出向量之间执行第一个双向搜索以识别数据通路中的门。然后构建包括所识别的门的网络流，并且将最小成本最大流算法应用于网络流以导出输入向量和输出向量之间的匹配比特对。接下来，通过在输入向量中的起始位和每个匹配位对的输出向量中的结束位之间执行第二双向搜索来确定数据通路位片。

9. 发明授权

US08516412B2 Soft hierarchy-based physical synthesis for large-scale, high-performance circuits 失效
标题翻译：用于大规模，高性能电路的基于层次结构的物理综合
公开(公告)号：US08516412B2
公开(公告)日：2013-08-20
申请号：US13222928
申请日：2011-08-31
申请人： Minsik Cho , Alvan W. Ng , Ruchir Puri , Haoxing Ren , Hua Xiang , Matthew M. Ziegler
发明人： Minsik Cho , Alvan W. Ng , Ruchir Puri , Haoxing Ren , Hua Xiang , Matthew M. Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/505
摘要： In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.
摘要翻译：在一个实施例中，本发明是用于大规模，高性能电路的基于层次的软合成的方法和装置。用于物理地合成集成电路的设计的方法的一个实施例包括将设计的逻辑描述编译成扁平网表，从扁平化网表中提取软层次，其中软层次结构定义了裸片上的边界，集成电路被允许移动，并且根据软层次将集成电路的单元放置在管芯上。

10. 发明授权

US08261226B1 Network flow based module bottom surface metal pin assignment 有权
标题翻译：网络流量模块底面金属引脚分配
公开(公告)号：US08261226B1
公开(公告)日：2012-09-04
申请号：US13187196
申请日：2011-07-20
申请人： Wiren Dale Becker , Ruchir Puri , Haoxing Ren , Hua Xiang , Tingdong Zhou
发明人： Wiren Dale Becker , Ruchir Puri , Haoxing Ren , Hua Xiang , Tingdong Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/08
摘要： A scaled network flow graph is constructed, including a plurality of nodes and a plurality of edges. The plurality of nodes correspond to: (i) a pseudo device pin node for each pair of corresponding paired device pins; (ii) a pseudo bottom surface metal node for each pair of bottom surface metal pins on each of multiple routing layers; (iii) a source node connected to each of the pseudo device pin nodes; (iv) a sub-sink node for each pair of the paired bottom surface metal pins (each of the sub-sink nodes is connected to corresponding ones of the pseudo bottom surface metal nodes for each of the pairs of bottom surface metal pins on each of the multiple routing layers); and (v) a sink node connected to the sub-sink nodes. A capacity and a cost are assigned to each of the edges of the scaled network flow graph. A min-cost-max-flow technique is applied to the scaled network flow graph with the assigned capacities and costs to obtain an optimal flow solution. The paired bottom surface metal pins are assigned to the corresponding paired device pins, and routing connections there-between are assigned, in accordance with the optimal flow solution. A technique for use in the absence of pairing constraints is also provided, as is a pin-pairing technique.
摘要翻译：构建了缩放的网络流程图，包括多个节点和多个边缘。多个节点对应于：（i）每对对应的配对设备引脚的伪器件引脚节点; （ii）在多个路由层中的每一个上的每对底表面金属销的伪底面金属节点; （iii）连接到每个伪器件引脚节点的源节点; （iv）每对成对的底表面金属销（每个子汇点中的每一个连接到每个底面表面金属节点中的每个底表面金属节点的子汇点）的多个路由层）; 和（v）连接到子汇点节点的汇聚节点。容量和成本被分配给缩放的网络流程图的每个边缘。最小成本最大流技术应用于具有分配容量和成本的缩放网络流图，以获得最佳流解决方案。配对的底面金属针脚被分配给相应的配对器件引脚，并且根据最佳流量解决方案分配其间的路由连接。还提供了在没有配对约束的情况下使用的技术，引脚配对技术也是如此。

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