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1. 发明申请

US20080246142A1 Heat dissipation unit and a semiconductor package that has the heat dissipation unit 审中-公开
标题翻译：散热单元和具有散热单元的半导体封装
公开(公告)号：US20080246142A1
公开(公告)日：2008-10-09
申请号：US12080798
申请日：2008-04-04
申请人： Jeng-Yuan Lai , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Jeng-Yuan Lai , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/367
CPC分类号： H01L23/4334 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process.
摘要翻译：公开了一种散热单元和具有该散热单元的半导体封装。半导体封装包括载体; 电子部件，其安装在所述载体上并与其电连接; 散热单元，其包括附接到所述电子部件的平坦部分，连接到所述平坦部分的延伸部分和连接到所述延伸部分的散热部分; 以及封装电子部件和散热部的密封剂，其中应力释放部至少设置在延伸部和平坦部之间的交叉角处，以防止在热冲压加工中由于集中应力而形成突起从而保持平坦部分的平坦度，并且进一步防止电子部件的电路在模制过程中由于在电子部件和平坦部分之间产生的接触点而损坏。

2. 发明申请

US20080277786A1 Semiconductor package substrate 审中-公开
标题翻译：半导体封装基板
公开(公告)号：US20080277786A1
公开(公告)日：2008-11-13
申请号：US12156874
申请日：2008-06-05
申请人： Chun-Lung Chen , Yu-Po Wang , Jeng-Yuan Lai , Cheng-Hsu Hsiao
发明人： Chun-Lung Chen , Yu-Po Wang , Jeng-Yuan Lai , Cheng-Hsu Hsiao
IPC分类号： H01L23/48
CPC分类号： H05K1/115 , H01L23/3677 , H01L23/49822 , H01L24/16 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2924/00011 , H01L2924/00014 , H01L2924/15174 , H01L2924/15311 , H05K1/0206 , H05K1/112 , H05K2201/09627 , H05K2201/0979 , H05K2201/10674 , H01L2224/0401
摘要： A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate.
摘要翻译：半导体封装基板包括具有彼此相对的上表面和下表面的主体，形成在主体中的多个电路层，形成在主体的上表面上的多个焊盘，以及多个焊球衬垫形成在身体的下表面上。每个焊盘通过设置在电路层之间的电路层和导电结构电连接到焊球之一，其中电路层和导电结构被配置为以扇出方式向外扩展，以便提供电路层之间的距离更靠近主体的下表面的空间更多，使得焊料焊盘 - 焊球焊盘电连接的一部分可以包括形成在该空间中的多个平行连接的导电结构，从而增强导热通道和效果的散热而不必在基板的表面上设置更多的焊盘。

3. 发明申请

US20090008801A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090008801A1
公开(公告)日：2009-01-08
申请号：US12217365
申请日：2008-07-02
申请人： Jeng-Yuan Lai , Chien-Ping Huang , Chun-Chi Ke , Yu-Po Wang , Chiao-Hung Yen
发明人： Jeng-Yuan Lai , Chien-Ping Huang , Chun-Chi Ke , Yu-Po Wang , Chiao-Hung Yen
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H05K1/0206 , H01L21/50 , H01L21/563 , H01L23/3677 , H01L23/3735 , H01L23/4985 , H01L24/17 , H01L24/32 , H01L2224/05001 , H01L2224/05026 , H01L2224/05027 , H01L2224/05572 , H01L2224/05644 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H05K1/0209 , H05K1/189 , H05K2201/09781 , H05K2201/10674 , H01L2924/00 , H01L2924/00014
摘要： This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer.
摘要翻译：本发明公开了一种半导体器件及其制造方法。该方法包括提供具有第一表面和与其相对的第二表面的柔性载体板; 在柔性载体板的第一表面上形成金属引线层和第一散热金属层，并在柔性载体板的第二表面上形成第二散热金属层; 提供具有活性表面和相对的非活性表面的芯片，其中在芯片的有源表面上形成多个焊盘，每个焊盘在其上形成金属凸块，并且在金属引线的对应位置在与第一散热金属层的位置对应的金属凸块之间形成有散热凸块。

4. 发明申请

US20080017983A1 Flip-chip semiconductor package and chip carrier thereof 有权
标题翻译：倒装芯片半导体封装及其芯片载体
公开(公告)号：US20080017983A1
公开(公告)日：2008-01-24
申请号：US11880467
申请日：2007-07-20
申请人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/48
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/351 , H01L2924/00
摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
摘要翻译：本发明公开了一种倒装芯片半导体封装及其芯片载体。芯片载体包括围绕芯片安装区域形成的凹槽。槽可以沿着芯片安装区域的周边或其拐角处形成。凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

5. 发明授权

US08207620B2 Flip-chip semiconductor package and chip carrier for preventing corner delamination 有权
标题翻译：倒装芯片半导体封装和芯片载体，用于防止角分层
公开(公告)号：US08207620B2
公开(公告)日：2012-06-26
申请号：US11880467
申请日：2007-07-20
申请人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/29
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/351 , H01L2924/00
摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
摘要翻译：本发明公开了一种倒装芯片半导体封装及其芯片载体。芯片载体包括围绕芯片安装区域形成的凹槽。槽可以沿着芯片安装区域的周边或其拐角处形成。凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

6. 发明申请

US20070262444A1 Semiconductor device and chip structure thereof 审中-公开
标题翻译：半导体器件及其芯片结构
公开(公告)号：US20070262444A1
公开(公告)日：2007-11-15
申请号：US11800451
申请日：2007-05-04
申请人： Yung-Chang Chen , Yuan-Lin Tzeng , Ming-Tsung Wang , Jeng-Yuan Lai , Cheng-Hsu Hsiao
发明人： Yung-Chang Chen , Yuan-Lin Tzeng , Ming-Tsung Wang , Jeng-Yuan Lai , Cheng-Hsu Hsiao
IPC分类号： H01L23/34
CPC分类号： H01L23/42 , H01L21/563 , H01L21/78 , H01L29/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/10158 , H01L2924/15311 , H01L2924/16152 , H01L2224/05599
摘要： A semiconductor device, a chip structure thereof, and a method for fabricating the same are proposed. The method involves cutting a wafer with an array of chips twice so as to separate the chips and to form a chip structure. The first cutting is wider than the second cutting, and both are performed on an inactive surface of each of the chips. The chip structure includes a protruding portion formed on the inactive surface. The chip structure is electrically connected to a substrate by conductive bumps in a flip-chip manner and mounted with a heat sink. A decrease in contact area between the chip and the heat sink reduces warpage caused to the semiconductor device by thermal stress, thus preventing delamination of the heat sink and cracking of the conductive bumps, and reducing the expense and time spent on finding suitable underfill materials.
摘要翻译：提出了一种半导体器件及其芯片结构及其制造方法。该方法包括用芯片阵列切割晶片两次以分离芯片并形成芯片结构。第一切割比第二切割宽，并且都在每个切屑的非活性表面上进行。芯片结构包括形成在非活性表面上的突出部分。芯片结构通过导电凸块以倒装芯片方式电连接到基板，并安装有散热片。芯片和散热片之间的接触面积的减小减少了热应力对半导体器件产生的翘曲，从而防止了散热器的分层和导电凸块的破裂，并且降低了在寻找合适的底部填充材料上花费的花费和时间。

7. 发明授权

US06369455B1 Externally-embedded heat-dissipating device for ball grid array integrated circuit package 有权
标题翻译：外置嵌入式散热装置，用于球栅阵列集成电路封装
公开(公告)号：US06369455B1
公开(公告)日：2002-04-09
申请号：US09545357
申请日：2000-04-07
申请人： Tzong-Da Ho , Chien-Ping Huang , Jeng-Yuan Lai
发明人： Tzong-Da Ho , Chien-Ping Huang , Jeng-Yuan Lai
IPC分类号： H01L2328
CPC分类号： H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00014 , H01L2924/00 , H01L2924/00015 , H01L2924/00012
摘要： An externally-embedded heat-dissipating device is designed for use with a BGA (Ball Grid Array) IC package for dissipating the IC-produced heat during operation to the atmosphere. that can help further increase the efficiency of heat dissipation from the BGA IC package. The heat-dissipating device is characterized in that it can be externally embedded in the top surface of the encapsulant without having to be supported on the substrate, and also in that it can help reduce the heat path from the IC chip to the heat-dissipating device so that heat-dissipation efficiency can be further increased as compared to the prior art. Further, the heat-dissipating device can help reduce manufacture cycle time and cost and also help prevent delamination, flash, and popcorn effect that would otherwise occur in the case of the prior art. It also can help save layout space over the substrate for compact design of the package. Overall speaking, the proposed heat-dissipating device is more advantageous to use than the prior art.
摘要翻译：外部嵌入散热装置设计用于BGA（球栅阵列）IC封装，用于在大气中运行时散发IC产生的热量。这有助于进一步提高BGA IC封装的散热效率。散热装置的特征在于，其可以外部嵌入密封剂的顶表面，而不必被支撑在基板上，并且还可以帮助减少从IC芯片到散热的热路径装置，使得与现有技术相比可以进一步提高散热效率。此外，散热装置有助于减少制造周期的时间和成本，并且还有助于防止在现有技术的情况下会发生的分层，闪光和爆米花效应。它还可以帮助节省基板上的布局空间，实现封装的紧凑设计。总体而言，所提出的散热装置比现有技术更有利于使用。

8. 发明授权

US06246115B1 Semiconductor package having a heat sink with an exposed surface 有权
标题翻译：具有具有暴露表面的散热器的半导体封装
公开(公告)号：US06246115B1
公开(公告)日：2001-06-12
申请号：US09425145
申请日：1999-10-21
申请人： Tom Tang , Chien Ping Huang , Kevin Chiang , Jeng-Yuan Lai , Candy Tien , Vicky Liu
发明人： Tom Tang , Chien Ping Huang , Kevin Chiang , Jeng-Yuan Lai , Candy Tien , Vicky Liu
IPC分类号： H01L2310
CPC分类号： H01L21/565 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit package with a fully-exposed heat sink is provided. The integrated circuit package includes a substrate having a first side being formed with first conductive traces and a second side being formed with second conductive traces. At least one chip is mounted on the substrate and electrically connected to the first conductive traces. A plurality of solder balls are provided at the terminal ends of the second conductive traces to allow external connection of the chip. The fully-exposed heat sink is mounted on the substrate. The heat sink is formed with a plurality of supportive legs arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a cavity in a mold used to form an encapsulant for enclosing the chip. A plurality of positioning tongues are formed on the heat sink for securing the heat sink in position when performing a molding process for forming the encapsulant. With this integrated circuit package, no jig is required in the assembly of the integrated circuit package. Moreover, since there is no need to use adhesives to adhere the supportive legs onto the substrate, the integrated circuit package would not suffer from delamination as in the case of the prior art. The fully-exposed heat sink allows an increased heat-dissipating efficient as compared to the prior art.
摘要翻译：提供了一个具有完全暴露的散热器的集成电路封装。集成电路封装包括具有形成有第一导电迹线的第一侧的基板，和形成有第二导电迹线的第二侧。至少一个芯片安装在基板上并电连接到第一导电迹线。多个焊球设置在第二导电迹线的末端，以允许芯片的外部连接。完全曝光的散热器安装在基板上。散热器形成有多个支撑腿，其布置成允许散热器的底表面与芯片分离，并且散热器的顶表面紧密地附接到模具中的空腔中用于形成封装芯片的密封剂。多个定位舌片形成在散热器上，用于在执行用于形成密封剂的成型工艺时将散热器固定就位。使用该集成电路封装，集成电路封装的组装中不需要夹具。此外，由于不需要使用粘合剂将支撑腿粘附到基板上，所以与现有技术的情况相同，集成电路封装不会遭受分层。与现有技术相比，完全暴露的散热器允许增加散热效率。

9. 发明授权

US08304665B2 Package substrate having landless conductive traces 有权
标题翻译：封装衬底具有无地导电迹线
公开(公告)号：US08304665B2
公开(公告)日：2012-11-06
申请号：US12266674
申请日：2008-11-07
申请人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
发明人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
IPC分类号： H05K1/11 , H05K1/09 , H01R9/00
CPC分类号： H05K1/116 , H05K1/114 , H05K2201/09545 , H05K2201/09563
摘要： A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
摘要翻译：提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与电镀通孔破裂。

10. 发明申请

US20090283303A1 PACKAGE SUBSTRATE HAVING LANDLESS CONDUCTIVE TRACES 有权
标题翻译：具有无轨导线的封装基板
公开(公告)号：US20090283303A1
公开(公告)日：2009-11-19
申请号：US12266674
申请日：2008-11-07
申请人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
发明人： Chiang-Cheng Chang , Yen-Ping Wang , Don-Son Jiang , Jeng-Yuan Lai , Yu-Po Wang
IPC分类号： H05K1/09
CPC分类号： H05K1/116 , H05K1/114 , H05K2201/09545 , H05K2201/09563
摘要： A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
摘要翻译：提出了具有无地导电迹线的封装衬底，其包括形成在其中的多个电镀通孔的芯层和形成在芯层的至少表面上的多个导电迹线。每个导电迹线具有连接端，接合焊盘端和连接连接端和接合焊盘端的基体，导电迹线通过连接端电连接到相应的一个电镀通孔，以及连接端具有大于基体的宽度，但不大于电镀通孔的直径，从而增加导电迹线和电镀通孔之间的接触面积，并且防止导电迹线的接触表面与电镀通孔破裂。

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