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1. 发明授权

US5633605A Dynamic bus with singular central precharge 失效
标题翻译：具有单中心预充电的动态总线
公开(公告)号：US5633605A
公开(公告)日：1997-05-27
申请号：US450764
申请日：1995-05-24
申请人： Jeffrey S. Zimmerman , John A. Fifield , Christopher P. Miller , Robert E. Busch
发明人： Jeffrey S. Zimmerman , John A. Fifield , Christopher P. Miller , Robert E. Busch
IPC分类号： G06F3/00 , G06F13/40 , H03K19/0185 , H03K19/0944 , H03K19/096
CPC分类号： G06F13/4077
摘要： A dynamic bus system with a central precharge device is disclosed that utilizes a controller circuit with a one-shot generator and write synchronizing circuits in combination with logic output modules having pull-up/down devices. The issuance of the output enable (OE) signals is interlocked with the turn-off of the precharge. Thus, data is written to the dynamic bus only when the precharge device is inactive, avoiding bus collisions. The resulting circuitry not only ensures the precharging of the bus before the data write to the bus, but will allow the synchronized OE signals to be issued during the same clock phase as the precharge signal.
摘要翻译：公开了一种具有中央预充电装置的动态总线系统，其利用具有单触发发生器的控制器电路和与具有上拉/下拉器件的逻辑输出模块相结合的写入同步电路。输出使能（OE）信号的发出与预充电的关断互锁。因此，仅当预充电设备处于非活动状态时才将数据写入动态总线，避免总线冲突。所产生的电路不仅可以确保在对总线的数据写入之前总线的预充电，而且允许在与预充电信号相同的时钟相位期间发出同步的OE信号。

2. 发明授权

US06442055B1 System and method for conserving power in a content addressable memory by providing an independent search line voltage 有权
标题翻译：通过提供独立的搜索线电压来节省内容可寻址存储器中的功率的系统和方法
公开(公告)号：US06442055B1
公开(公告)日：2002-08-27
申请号：US10016025
申请日：2001-12-12
申请人： Robert E. Busch , Kevin A. Batson
发明人： Robert E. Busch , Kevin A. Batson
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A system and method is disclosed for operating a content addressable memory (CAM) within an integrated circuit using search signals at search input voltages which are substantially independent from an operating voltage of the CAM. A method is disclosed in which search signals are input to CAM cells of the CAM at search input voltages which are substantially independent of an operating voltage of storage elements within the CAM cells. A match signal is output upon detecting a matching condition between the search signals and data stored in the storage elements. The search input voltage can be within about 0.2V above a threshold voltage of a search input device of the CAM memory cell. Search input devices can be selected to have a lower threshold voltage than other devices included within the CAM cell.
摘要翻译：公开了一种用于在搜索输入电压下使用基本上独立于CAM的工作电压的搜索信号来操作集成电路内的内容可寻址存储器（CAM）的系统和方法。公开了一种方法，其中搜索信号以基本上独立于CAM单元内的存储元件的工作电压的搜索输入电压输入到CAM的CAM单元。在检测到搜索信号和存储在存储元件中的数据之间的匹配条件时输出匹配信号。搜索输入电压可以在CAM存储器单元的搜索输入装置的阈值电压以上约0.2V内。可以选择搜索输入设备以具有比包括在CAM单元内的其它设备更低的阈值电压。

3. 发明授权

US06208572B1 Semiconductor memory device having resistive bitline contact testing 失效
标题翻译：具有电阻位线接触测试的半导体存储器件
公开(公告)号：US06208572B1
公开(公告)日：2001-03-27
申请号：US09592055
申请日：2000-06-12
申请人： R. Dean Adams , Robert E. Busch , Harold Pilo , George E. Rudgers
发明人： R. Dean Adams , Robert E. Busch , Harold Pilo , George E. Rudgers
IPC分类号： G11C2900
CPC分类号： G11C29/50
摘要： A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
摘要翻译：具有电阻位线接触测试的半导体存储器件包括存储单元和用于同时激活两个相邻存储器单元的字线逻辑器件。两个相邻的存储单元同时被激活，以允许更高的电流通过位线接点来改善电阻位线触点的检测。还可以包括测试单元以测试位线接触的完整性。

4. 发明授权

US07117400B2 Memory device with data line steering and bitline redundancy 失效
标题翻译：具有数据线转向和位线冗余的存储器件
公开(公告)号：US07117400B2
公开(公告)日：2006-10-03
申请号：US10065723
申请日：2002-11-13
申请人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch , Fred J. Towler , Reid A. Wistort
发明人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch , Fred J. Towler , Reid A. Wistort
IPC分类号： G06F11/20 , G11C11/4094 , G11C15/00 , G11C15/04
CPC分类号： G11C29/832 , G11C15/00 , G11C29/848
摘要： An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.
摘要翻译：一种集成电路，包括：一组位线; 一组数据线; 用于基于转向信号将每个相应数据线耦合到第一相应位线或第二相应位线的装置，所述第二相应位线与所述第一相应位线相邻; 以及用于在数据线耦合到第二位线之后将第一相应位线保持在期望电位的装置。

5. 发明授权

US06201750B1 Scannable fuse latches 失效
标题翻译：可擦除保险丝锁存器
公开(公告)号：US06201750B1
公开(公告)日：2001-03-13
申请号：US09598427
申请日：2000-06-21
申请人： Robert E. Busch , Fred J. Towler , Reid A. Wistort
发明人： Robert E. Busch , Fred J. Towler , Reid A. Wistort
IPC分类号： G11C700
CPC分类号： G01R31/318541 , G11C17/16 , G11C17/18
摘要： Scannable fuse latches are provided that can override current fuse values, read current fuse values, and latch current fuse values. Using the scannable fuse latches of the current invention allows current fuse values to be overridden, which can be important in testing and failure analysis to place the integrated circuit in a known state. The scannable fuse latches of the current invention also allow current fuse values to be read. This aids failure analysis because the current state of the failed integrated circuit can be determined. Finally, the scannable fuse latches of the present invention allow the current state of fuses to be latched and provided to a core of an integrated circuit.
摘要翻译：提供了可以提供可以覆盖当前熔丝值，读取当前熔丝值和锁存当前熔丝值的可擦除保险丝锁存器。使用本发明的可扫描的熔丝锁存器允许覆盖当前熔丝值，这对于将集成电路置于已知状态的测试和故障分析中可能是重要的。本发明的可扫描的熔丝锁存器还允许读取当前熔丝值。这有助于故障分析，因为可以确定故障集成电路的当前状态。最后，本发明的可扫描熔丝锁存器允许保险丝的当前状态被锁存并提供给集成电路的核心。

6. 发明授权

US5036495A Multiple mode-set for IC chip 失效
标题翻译： IC芯片多模模式
公开(公告)号：US5036495A
公开(公告)日：1991-07-30
申请号：US469880
申请日：1989-12-28
申请人： Robert E. Busch , William P. Hovis , Theodore M. Redman , Endre P. Thoma , James A. Yankosky
发明人： Robert E. Busch , William P. Hovis , Theodore M. Redman , Endre P. Thoma , James A. Yankosky
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C11/4076
CPC分类号： G11C7/1045 , G11C11/4076 , G11C7/22
摘要： A method and device for setting at least three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

7. 发明授权

US06791855B2 Redundant array architecture for word replacement in CAM 有权
标题翻译： CAM中字替换的冗余阵列架构
公开(公告)号：US06791855B2
公开(公告)日：2004-09-14
申请号：US10641753
申请日：2003-08-14
申请人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
发明人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
IPC分类号： G11C1500
CPC分类号： G11C29/816 , G11C15/00
摘要： The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
摘要翻译：本发明提供了一种存储器架构，其允许通过已经提供在芯片上的未增加芯片尺寸的备用元件进行存储器检查和替换缺陷字。本发明的方法使用单独的冗余阵列架构来提供地址转换，使得冗余条目被表示为正在替换的正确条目索引。

8. 发明授权

US06687144B2 High reliability content-addressable memory using shadow content-addressable memory 失效
标题翻译：高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存
公开(公告)号：US06687144B2
公开(公告)日：2004-02-03
申请号：US10430671
申请日：2003-05-06
申请人： Kevin A. Batson , Geordie M Braceras , Robert E. Busch , Gary S. Koch
发明人： Kevin A. Batson , Geordie M Braceras , Robert E. Busch , Gary S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译：使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容和可寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。阴影CAM与主CAM并行写入，读取和搜索。比较并行搜索的搜索结果，如果相同，则声明为有效。如果搜索结果不相等，则会启动纠正措施。高可靠性内容寻址存储器可以与或不与优先编码器一起使用。

9. 发明授权

US06501675B2 Alternating reference wordline scheme for fast DRAM 有权
标题翻译：快速DRAM的交替参考字线方案
公开(公告)号：US06501675B2
公开(公告)日：2002-12-31
申请号：US09854987
申请日：2001-05-14
申请人： Harold Pilo , Robert E. Busch
发明人： Harold Pilo , Robert E. Busch
IPC分类号： G11C1124
CPC分类号： G11C8/14 , G11C7/14 , G11C11/4099
摘要： A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycle's reference bitline generation.
摘要翻译：快速DRAM存储器使用地面感测，而不是传统的Vdd / 2感测。所选择的DRAM单元连接到位线真（BLT）或位线补码（BLC）。在每个循环开始时，BLT和BLC恢复到地电位。为每个位线提供一对交替参考单元。当所选择的DRAM单元连接到BLT或BLC时，该对中的第一参考单元连接到另一位线，以向可与所选择的DRAM单元提供的电压进行比较的另一位线提供参考电压。在使用相同位线的后续周期中，使用该对中的第二参考单元。因此，在开始下一个周期之前，不需要等待第一个参考单元进行充电。该对中的第一和第二参考单元之间的切换以这种方式交替地产生更快的周期时间。可以隐藏参考单元的回写，因为替代单元可用于下一循环的参考位线生成。

10. 发明授权

US5276846A Fast access memory structure 失效
标题翻译：快速存取存储器结构
公开(公告)号：US5276846A
公开(公告)日：1994-01-04
申请号：US829608
申请日：1992-01-30
申请人： Frederick J. Aichelmann, Jr. , Bruce E. Bachman , Robert E. Busch , Theodore M. Redman , Endre P. Thoma
发明人： Frederick J. Aichelmann, Jr. , Bruce E. Bachman , Robert E. Busch , Theodore M. Redman , Endre P. Thoma
IPC分类号： G11C7/10 , G06F12/06
CPC分类号： G11C7/1006
摘要： A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages. The memory chip also includes a gating structure for gating the respective groups of stages to the N data unit parallel output interface, the gating structure including at least a first gate circuit for gating in parallel the data units held in the first group of stages to the N data unit parallel output interface in accordance with a TOGGLE logic signal, and a second gate circuit for gating in parallel the data units held in the second group of stages to the N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.
摘要翻译：一种存储器芯片，包括被组织为保持多个单独的数据块的芯片存储器部分，每个数据块包含M个单独的数据单元; 用于寻址芯片存储器部分中的给定数据块的电路; 以及来自存储器芯片的N个数据单元芯片并行输出接口，其中N小于M，N大于1。存储器芯片还包括芯片寄存器，用于从芯片存储器部分接收所寻址的数据块的至少一部分，该部分包括P数据单元，其中P大于N，具有P寄存器级的芯片寄存器用于保持所述寻址数据块的P数据单元，其中所述P寄存器级被分组为至少第一和第二组级，其中没有一组级包括多于N个寄存器级，并且所述寄存器级组中的至少一个具有多个阶段。存储器芯片还包括用于将N个数据单元并行输出接口的各个级组门控的选通结构，门控结构至少包括第一门电路，用于并行地选通保持在第一组级中的数据单元 N数据单元并行输出接口，以及第二门电路，用于根据NOT TOGGLE逻辑信号并行地将保持在第二组级中的数据单元门控到N个数据单元并行输出接口。

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