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1. 发明授权

US06208572B1 Semiconductor memory device having resistive bitline contact testing 失效
标题翻译：具有电阻位线接触测试的半导体存储器件
公开(公告)号：US06208572B1
公开(公告)日：2001-03-27
申请号：US09592055
申请日：2000-06-12
申请人： R. Dean Adams , Robert E. Busch , Harold Pilo , George E. Rudgers
发明人： R. Dean Adams , Robert E. Busch , Harold Pilo , George E. Rudgers
IPC分类号： G11C2900
CPC分类号： G11C29/50
摘要： A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
摘要翻译：具有电阻位线接触测试的半导体存储器件包括存储单元和用于同时激活两个相邻存储器单元的字线逻辑器件。两个相邻的存储单元同时被激活，以允许更高的电流通过位线接点来改善电阻位线触点的检测。还可以包括测试单元以测试位线接触的完整性。

2. 发明授权

US06501675B2 Alternating reference wordline scheme for fast DRAM 有权
标题翻译：快速DRAM的交替参考字线方案
公开(公告)号：US06501675B2
公开(公告)日：2002-12-31
申请号：US09854987
申请日：2001-05-14
申请人： Harold Pilo , Robert E. Busch
发明人： Harold Pilo , Robert E. Busch
IPC分类号： G11C1124
CPC分类号： G11C8/14 , G11C7/14 , G11C11/4099
摘要： A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycle's reference bitline generation.
摘要翻译：快速DRAM存储器使用地面感测，而不是传统的Vdd / 2感测。所选择的DRAM单元连接到位线真（BLT）或位线补码（BLC）。在每个循环开始时，BLT和BLC恢复到地电位。为每个位线提供一对交替参考单元。当所选择的DRAM单元连接到BLT或BLC时，该对中的第一参考单元连接到另一位线，以向可与所选择的DRAM单元提供的电压进行比较的另一位线提供参考电压。在使用相同位线的后续周期中，使用该对中的第二参考单元。因此，在开始下一个周期之前，不需要等待第一个参考单元进行充电。该对中的第一和第二参考单元之间的切换以这种方式交替地产生更快的周期时间。可以隐藏参考单元的回写，因为替代单元可用于下一循环的参考位线生成。

3. 发明授权

US08611169B2 Fine granularity power gating 有权
标题翻译：细粒度电源门控
公开(公告)号：US08611169B2
公开(公告)日：2013-12-17
申请号：US13315604
申请日：2011-12-09
申请人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
发明人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C8/08 , G11C8/10
摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.
摘要翻译：描述了一种用于提供存储器阵列的精细粒度电源门控的方法。在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线存储器阵列中的剩余行被提供电源门控电压值。

4. 发明申请

US20120075919A1 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权
标题翻译：用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量
公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
申请人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译：在制造的SRAM中设置字线上电压的方法。在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

5. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

6. 发明授权

US07548080B2 Method and apparatus for burn-in optimization 失效
标题翻译：老化优化的方法和装置
公开(公告)号：US07548080B2
公开(公告)日：2009-06-16
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

7. 发明申请

US20090080276A1 Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits 审中-公开
标题翻译：用于CMOS电路中最小待机功率的温度偏置偏置
公开(公告)号：US20090080276A1
公开(公告)日：2009-03-26
申请号：US11859775
申请日：2007-09-23
申请人： Jin Cai , Randy William Mann , Harold Pilo
发明人： Jin Cai , Randy William Mann , Harold Pilo
IPC分类号： G05F1/567 , G11C7/04 , H03K17/16
CPC分类号： H03K19/0016 , H03K19/00369
摘要： A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals.
摘要翻译：公开了一种产生这种偏置电压的电路，当偏置电压由半导体芯片的大量多个器件接收时，在待机模式下，在任何特定的工作温度下都会降低功耗。所公开的电路包括至少一个监控FET，其保持在其截止状态，并且与大量多个FET器件具有共同的特性。检测监控FET的温度依赖性漏电流，并用于产生与泄漏电流成正比的偏置电压。该偏置电压由大型多个FET器件在其栅极电极或其主体端子上接收。

8. 发明授权

US07495950B2 Voltage controlled static random access memory 失效
标题翻译：电压控制静态随机存取存储器
公开(公告)号：US07495950B2
公开(公告)日：2009-02-24
申请号：US11926689
申请日：2007-10-29
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/413
摘要： A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
摘要翻译：包括多个SRAM单元，多个字线（WL0-WLN）和用于用字线电压信号（VWLP）驱动字线的电压调节器的静态随机存取存储器（SRAM）。确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL）对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

9. 发明申请

US20080219069A1 DEVICE THRESHOLD CALIBRATION THROUGH STATE DEPENDENT BURNIN 有权
标题翻译：通过状态相关燃烧器进行设备阈值校准
公开(公告)号：US20080219069A1
公开(公告)日：2008-09-11
申请号：US11684225
申请日：2007-03-09
申请人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
发明人： Igor Arsovski , Harold Pilo , Michael A. Ziegerhofer
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/028
摘要： Disclosed are embodiments of a method for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.
摘要翻译：公开了用于减少和/或消除错配的方法的实施例。这些实施例在芯片烧录之前对需要平衡状态的一个或多个电路子部件（例如，在每个存储器单元中的交叉耦合晶体管的偏置和/或存储器阵列中的读出放大器）进行采样，通过启动老化过程，在该过程中，单独选择的状态被应用于电路中的每个设备。这使得设备远离其优选的状态并且朝向平衡状态。在老化过程中定期重新评估偏差，以避免过度校正。通过使用这种方法，可以在存储器阵列中减少存储器单元和读出放大器的失配，从而导致较小的定时不确定性，因此更快的存储器。

10. 发明申请

US20080049534A1 Voltage Controlled Static Random Access Memory 失效
标题翻译：电压控制静态随机存取存储器
公开(公告)号：US20080049534A1
公开(公告)日：2008-02-28
申请号：US11923796
申请日：2007-10-25
申请人： John Fifield , Harold Pilo
发明人： John Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C11/413
摘要： A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines(WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
摘要翻译：一种静态随机存取存储器（SRAM），包括多个SRAM单元，多个字线（WL 0 -WLN）和用于用字线电压信号（VWLP）驱动字线的电压调节器。确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL）对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

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