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1. 发明授权

US06442055B1 System and method for conserving power in a content addressable memory by providing an independent search line voltage 有权
标题翻译：通过提供独立的搜索线电压来节省内容可寻址存储器中的功率的系统和方法
公开(公告)号：US06442055B1
公开(公告)日：2002-08-27
申请号：US10016025
申请日：2001-12-12
申请人： Robert E. Busch , Kevin A. Batson
发明人： Robert E. Busch , Kevin A. Batson
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A system and method is disclosed for operating a content addressable memory (CAM) within an integrated circuit using search signals at search input voltages which are substantially independent from an operating voltage of the CAM. A method is disclosed in which search signals are input to CAM cells of the CAM at search input voltages which are substantially independent of an operating voltage of storage elements within the CAM cells. A match signal is output upon detecting a matching condition between the search signals and data stored in the storage elements. The search input voltage can be within about 0.2V above a threshold voltage of a search input device of the CAM memory cell. Search input devices can be selected to have a lower threshold voltage than other devices included within the CAM cell.
摘要翻译：公开了一种用于在搜索输入电压下使用基本上独立于CAM的工作电压的搜索信号来操作集成电路内的内容可寻址存储器（CAM）的系统和方法。公开了一种方法，其中搜索信号以基本上独立于CAM单元内的存储元件的工作电压的搜索输入电压输入到CAM的CAM单元。在检测到搜索信号和存储在存储元件中的数据之间的匹配条件时输出匹配信号。搜索输入电压可以在CAM存储器单元的搜索输入装置的阈值电压以上约0.2V内。可以选择搜索输入设备以具有比包括在CAM单元内的其它设备更低的阈值电压。

2. 发明授权

US07117400B2 Memory device with data line steering and bitline redundancy 失效
标题翻译：具有数据线转向和位线冗余的存储器件
公开(公告)号：US07117400B2
公开(公告)日：2006-10-03
申请号：US10065723
申请日：2002-11-13
申请人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch , Fred J. Towler , Reid A. Wistort
发明人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch , Fred J. Towler , Reid A. Wistort
IPC分类号： G06F11/20 , G11C11/4094 , G11C15/00 , G11C15/04
CPC分类号： G11C29/832 , G11C15/00 , G11C29/848
摘要： An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.
摘要翻译：一种集成电路，包括：一组位线; 一组数据线; 用于基于转向信号将每个相应数据线耦合到第一相应位线或第二相应位线的装置，所述第二相应位线与所述第一相应位线相邻; 以及用于在数据线耦合到第二位线之后将第一相应位线保持在期望电位的装置。

3. 发明授权

US06791855B2 Redundant array architecture for word replacement in CAM 有权
标题翻译： CAM中字替换的冗余阵列架构
公开(公告)号：US06791855B2
公开(公告)日：2004-09-14
申请号：US10641753
申请日：2003-08-14
申请人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
发明人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
IPC分类号： G11C1500
CPC分类号： G11C29/816 , G11C15/00
摘要： The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.
摘要翻译：本发明提供了一种存储器架构，其允许通过已经提供在芯片上的未增加芯片尺寸的备用元件进行存储器检查和替换缺陷字。本发明的方法使用单独的冗余阵列架构来提供地址转换，使得冗余条目被表示为正在替换的正确条目索引。

4. 发明授权

US06687144B2 High reliability content-addressable memory using shadow content-addressable memory 失效
标题翻译：高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存
公开(公告)号：US06687144B2
公开(公告)日：2004-02-03
申请号：US10430671
申请日：2003-05-06
申请人： Kevin A. Batson , Geordie M Braceras , Robert E. Busch , Gary S. Koch
发明人： Kevin A. Batson , Geordie M Braceras , Robert E. Busch , Gary S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译：使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容和可寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。阴影CAM与主CAM并行写入，读取和搜索。比较并行搜索的搜索结果，如果相同，则声明为有效。如果搜索结果不相等，则会启动纠正措施。高可靠性内容寻址存储器可以与或不与优先编码器一起使用。

5. 发明授权

US06760881B2 Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) 有权
标题翻译：在基于DRAM的内容可寻址存储器（CAM）中组合刷新操作与奇偶校验的方法
公开(公告)号：US06760881B2
公开(公告)日：2004-07-06
申请号：US09981081
申请日：2001-10-16
申请人： Kevin A. Batson , Robert E. Busch , Albert M. Chu , Ezra D. B. Hall
发明人： Kevin A. Batson , Robert E. Busch , Albert M. Chu , Ezra D. B. Hall
IPC分类号： G11C2900
CPC分类号： G11C7/24 , G11C11/406 , G11C15/043
摘要： A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.
摘要翻译：公开了一种用于将刷新操作与用于基于DRAM的内容可寻址存储器（CAM）的奇偶验证相结合的方法。在本发明的示例性实施例中，该方法包括实现存储器刷新操作并检查CAM内包含的单词。确定该单词中包含的数据是否构成有效数据。如果单词中包含的数据不构成有效数据，则旁路奇偶校验。然而，如果单词中包含的数据确实构成有效数据，则实现奇偶校验验证。奇偶校验验证还包括读取单词中包含的数据，从包含在单词内的数据生成奇偶校验位，并将生成的奇偶校验位与先前存储的奇偶校验位进行比较。如果执行奇偶校验验证，并且如果生成的奇偶校验位与先前存储的奇偶校验位不匹配，则该单词中包含的数据无效。

6. 发明授权

US06728123B2 Redundant array architecture for word replacement in CAM 有权
公开(公告)号：US06728123B2
公开(公告)日：2004-04-27
申请号：US10123493
申请日：2002-04-15
申请人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
发明人： Kevin A. Batson , Robert E. Busch , Gary S. Koch , Fred J. Towler , Reid A. Wistort
IPC分类号： G11C1502
CPC分类号： G11C29/816 , G11C15/00
摘要： The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.

7. 发明授权

US06650561B2 High reliability content-addressable memory using shadow content-addressable memory 有权
标题翻译：高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存
公开(公告)号：US06650561B2
公开(公告)日：2003-11-18
申请号：US10059863
申请日：2002-01-30
申请人： Kevin A. Batson , Geordie M. Braceras , Robert E. Busch , Gary S. Koch
发明人： Kevin A. Batson , Geordie M. Braceras , Robert E. Busch , Gary S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译：使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。阴影CAM与主CAM并行写入，读取和搜索。比较并行搜索的搜索结果，如果相同，则声明为有效。如果搜索结果不相等，则会启动纠正措施。高可靠性内容寻址存储器可以与或不与优先编码器一起使用。

8. 发明授权

US06430073B1 Dram CAM cell with hidden refresh 有权
标题翻译：具有隐藏刷新功能的CAM CAM单元
公开(公告)号：US06430073B1
公开(公告)日：2002-08-06
申请号：US09730673
申请日：2000-12-06
申请人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch
发明人： Kevin A. Batson , Robert E. Busch , Garrett S. Koch
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.
摘要翻译：动态内容可寻址存储器（DCAM）单元拓扑，其包含较少的可以执行不会延迟或中断CAM搜索周期的存储数据的“隐藏”刷新，从而提供类似SCAM的性能。执行非破坏性读取操作，使得由于刷新读取操作而不必将所存储的数据写回。可以在读取操作之后，甚至在刷新数据被写回之前执行可靠的CAM搜索。可以在更新周期的未决期间对每个CAM条目执行软错误检测处理。 DCAM单元可用于数字系统，如数字计算机和网络路由器。

9. 发明授权

US06208572B1 Semiconductor memory device having resistive bitline contact testing 失效
标题翻译：具有电阻位线接触测试的半导体存储器件
公开(公告)号：US06208572B1
公开(公告)日：2001-03-27
申请号：US09592055
申请日：2000-06-12
申请人： R. Dean Adams , Robert E. Busch , Harold Pilo , George E. Rudgers
发明人： R. Dean Adams , Robert E. Busch , Harold Pilo , George E. Rudgers
IPC分类号： G11C2900
CPC分类号： G11C29/50
摘要： A semiconductor memory device having resistive bitline contact testing includes memory cells, and wordline logic devices for concurrently activating two adjacent memory cells. The two adjacent memory cells are activated concurrently to allow higher current through a bitline contact for improved detection of resistive bitline contacts. A test cell may also be included to test the integrity of the bitline contact.
摘要翻译：具有电阻位线接触测试的半导体存储器件包括存储单元和用于同时激活两个相邻存储器单元的字线逻辑器件。两个相邻的存储单元同时被激活，以允许更高的电流通过位线接点来改善电阻位线触点的检测。还可以包括测试单元以测试位线接触的完整性。

10. 发明授权

US06201750B1 Scannable fuse latches 失效
标题翻译：可擦除保险丝锁存器
公开(公告)号：US06201750B1
公开(公告)日：2001-03-13
申请号：US09598427
申请日：2000-06-21
申请人： Robert E. Busch , Fred J. Towler , Reid A. Wistort
发明人： Robert E. Busch , Fred J. Towler , Reid A. Wistort
IPC分类号： G11C700
CPC分类号： G01R31/318541 , G11C17/16 , G11C17/18
摘要： Scannable fuse latches are provided that can override current fuse values, read current fuse values, and latch current fuse values. Using the scannable fuse latches of the current invention allows current fuse values to be overridden, which can be important in testing and failure analysis to place the integrated circuit in a known state. The scannable fuse latches of the current invention also allow current fuse values to be read. This aids failure analysis because the current state of the failed integrated circuit can be determined. Finally, the scannable fuse latches of the present invention allow the current state of fuses to be latched and provided to a core of an integrated circuit.
摘要翻译：提供了可以提供可以覆盖当前熔丝值，读取当前熔丝值和锁存当前熔丝值的可擦除保险丝锁存器。使用本发明的可扫描的熔丝锁存器允许覆盖当前熔丝值，这对于将集成电路置于已知状态的测试和故障分析中可能是重要的。本发明的可扫描的熔丝锁存器还允许读取当前熔丝值。这有助于故障分析，因为可以确定故障集成电路的当前状态。最后，本发明的可扫描熔丝锁存器允许保险丝的当前状态被锁存并提供给集成电路的核心。

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