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1. 发明申请

US20050172194A1 REMOTE BIST HIGH SPEED TEST AND REDUNDANCY CALCULATION 有权
标题翻译：远程高速测试和冗余计算
公开(公告)号：US20050172194A1
公开(公告)日：2005-08-04
申请号：US10707971
申请日：2004-01-29
申请人： Jeffrey Dreibelbis , Kevin Gorman , Michael Nelms
发明人： Jeffrey Dreibelbis , Kevin Gorman , Michael Nelms
IPC分类号： G01R31/28 , G01R31/317 , G11C29/00 , G11C29/14 , G11C29/16 , G11C29/44
CPC分类号： G11C29/14 , G01R31/31724 , G01R31/3187 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/0401
摘要： Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.
摘要翻译：公开了一种用于嵌入式存储器阵列的混合内置自测（BIST）架构，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。独立的BIST逻辑控制器以较低的频率工作，并使用BIST指令集与多个嵌入式存储器阵列进行通信。一个高速测试逻辑块被并入被测试的每个嵌入式存储器阵列中，并以更高的频率在本地处理从独立BIST逻辑控制器接收的BIST指令。高速测试逻辑包括用于将BIST指令的频率从较低频率增加到较高频率的乘法器。独立的BIST逻辑控制器使多个嵌入式存储器阵列中的多个更高速的测试逻辑结构能够实现。

2. 发明申请

US20050120270A1 AUTOMATIC BIT FAIL MAPPING FOR EMBEDDED MEMORIES WITH CLOCK MULTIPLIERS 失效
标题翻译：具有时钟乘法器的嵌入式存储器的自动位失效映射
公开(公告)号：US20050120270A1
公开(公告)日：2005-06-02
申请号：US10707071
申请日：2003-11-19
申请人： Darren Anand , Kevin Gorman , Michael Nelms
发明人： Darren Anand , Kevin Gorman , Michael Nelms
IPC分类号： G06F11/00 , G11C29/00 , G11C29/14 , G11C29/56
CPC分类号： G11C29/56 , G11C29/14 , G11C29/56008 , G11C2029/5604
摘要： A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.
摘要翻译：位故障映射电路通过利用从低速自动测试设备（ATE）测试器产生的高速倍增时钟，精确地生成诸如DRAM的嵌入式存储器的位故障映射。该电路在ATE测试仪，被测嵌入式内存，内置自检（BIST）和内置冗余分析（BIRA）之间进行通信。通过在遇到失败时暂停BIST测试电路，即BIST预期数据与从阵列读取的实际数据之间的不匹配，然后移位位故障数据，提供嵌入式DRAM存储器的精确位故障映射使用低速ATE测试仪时钟关闭芯片。此后，通过使用高速内部时钟再次运行BIST，从故障点恢复高速测试，以提供高速位Fail Map。

3. 发明申请

US20050160310A1 Integrated Redundancy Architecture and Method for Providing Redundancy Allocation to an Embedded Memory System 失效
标题翻译：集成冗余架构和方法为嵌入式存储系统提供冗余分配
公开(公告)号：US20050160310A1
公开(公告)日：2005-07-21
申请号：US10707797
申请日：2004-01-13
申请人： Wayne Ellis , Kevin Gorman
发明人： Wayne Ellis , Kevin Gorman
IPC分类号： G06F11/00 , G11C29/00 , G11C29/44
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/74
摘要： An integrated redundancy architecture for an embedded memory system whereby a third memory element is added to the redundancy architecture such that all row and column fails may be stored in real-time. Architecture (20) includes a first memory element (22) (FME 22) having a register (24), a second memory element (26) (SME 26) having a register (28), a third memory element (30) (TME 30) having a register (32), and a finite state machine (34) (FSM 34) having a decision algorithm (36). FME (22), SME (26), TME (30), and FSM (34) are electrically connected to a built-in self-test (BIST) module (38). BIST module (38) outputs failed row and column addresses (40), also referred to as “fails,” for rows and columns that are identified as defective during the BIST to the memory elements and FSM (34). FSM (34) allocates redundancy resources of the memory system according to decision algorithm (36).
摘要翻译：用于嵌入式存储器系统的集成冗余架构，由此第三存储器元件被添加到冗余架构，使得可以实时地存储所有行和列失败。架构（20）包括具有寄存器（24）的第一存储器元件（22）（FME 22），具有寄存器（28）的第二存储元件（26）（SME 26），第三存储器元件（30）具有寄存器（32）和具有判定算法（36）的有限状态机（34）（FSM 34）。 FME（22），SME（26），TME（30）和FSM（34）电连接到内置自检（BIST）模块（38）。对于在存储元件和FSM（34）的BIST期间被识别为有缺陷的行和列，BIST模块（38）输出失败的行和列地址（40），也称为“失败”。 FSM（34）根据决策算法（36）分配存储器系统的冗余资源。

4. 发明申请

US20070233568A1 Microtransactions Using Points Over Electronic Networks 审中-公开
标题翻译：使用电子网络点的微交易
公开(公告)号：US20070233568A1
公开(公告)日：2007-10-04
申请号：US11683820
申请日：2007-03-08
申请人： Robin Pou , Brad Edmonson , Dave Jaworski , Kevin Gorman
发明人： Robin Pou , Brad Edmonson , Dave Jaworski , Kevin Gorman
IPC分类号： G06Q30/00 , G06Q40/00
CPC分类号： G06Q30/0603 , G06Q20/10 , G06Q30/0226 , G06Q30/0601
摘要： In some implementations, methods and apparatus, including computer program products, facilitate microtransactions over electronic networks by providing an electronic points currency that can be purchased in bulk and used for purchasing goods and services in microtransactions. In a typical implementation, points may be purchased in bulk quantities that have a value that is large relative to the price of a single product that may be purchased in a microtransaction. A microtransaction vendor may offer products for sale at a discount by setting a first price for purchases made with a credit card and a second lower price for purchases made using points.
摘要翻译：在一些实施方式中，包括计算机程序产品的方法和装置通过提供可以批量购买并用于在微交易中购买商品和服务的电子点货币来促进电子网络的微交易。在典型的实施中，点数可以批量购买，其价值相对于可以在微交易中购买的单一产品的价格较大。微交易供应商可以通过设置使用信用卡进行购买的第一个价格以及使用点购买的第二个较低的价格，以折扣的方式提供销售产品。

5. 发明申请

US20070230260A1 AUTOMATIC SHUTDOWN OR THROTTLING OF A BIST STATE MACHINE USING THERMAL FEEDBACK 失效
标题翻译：使用热反馈自动关机或弯曲状态机
公开(公告)号：US20070230260A1
公开(公告)日：2007-10-04
申请号：US11278238
申请日：2006-03-31
申请人： Kevin Gorman , Emory Keller , Michael Ouellette
发明人： Kevin Gorman , Emory Keller , Michael Ouellette
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/16 , G11C2029/5002
摘要： A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.
摘要翻译：内置自测试（BIST）状态机，提供与位于BIST测试操作所在电路附近的热传感器设备相关的BIST测试操作。热传感器装置将感测到的当前温度值与预定温度阈值进行比较，并确定是否超过预定阈值。 BIST控制元件响应于满足或超过所述预定温度阈值而暂停BIST测试操作，并且当当前温度值归一化或降低时，启动BIST测试操作的恢复。响应于确定满足或超过预定温度阈值，BIST测试方法实现了减轻超过温度阈值条件的步骤。这些步骤包括：忽略可疑电路的BIST结果，或通过使BIST状态机进入等待状态，并在等待状态下调整可疑电路的工作参数。

6. 发明申请

US20070226567A1 HIGH SPEED BIST UTILIZING CLOCK MULTIPLICATION 审中-公开
标题翻译：使用时钟多路复用的高速BIST
公开(公告)号：US20070226567A1
公开(公告)日：2007-09-27
申请号：US11277310
申请日：2006-03-23
申请人： Kevin Gorman , Gerald Pomichter
发明人： Kevin Gorman , Gerald Pomichter
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/3187 , G11C7/02 , G11C29/12015 , G11C29/14 , G11C2207/104
摘要： A system and method of performing high speed built-in self test (BIST) using clock multiplication. A system is provided for testing a high speed integrated circuit using a low speed tester, comprising: a built-in self test (BIST) engine coupled to the integrated circuit; a clock multiplier adapted to derive a high speed clock signal from a clock signal supplied by the low speed tester, wherein the high speed clock signal drives the testing of the high speed integrated circuit; and an edge shaper coupled to the clock multiplier and the BIST engine, the edge shaper configured to output a plurality of different shaped clock signals.
摘要翻译：使用时钟相乘执行高速内置自检（BIST）的系统和方法。提供一种用于使用低速测试仪测试高速集成电路的系统，包括：耦合到集成电路的内置自测试（BIST）引擎; 适用于从低速测试仪提供的时钟信号导出高速时钟信号的时钟倍频器，其中高速时钟信号驱动高速集成电路的测试; 以及耦合到时钟倍增器和BIST引擎的边缘整形器，边缘整形器被配置为输出多个不同形状的时钟信号。

7. 发明授权

US08661734B2 Window assembly with a sliding member and a security member having a ventilation portion 有权
标题翻译：具有滑动构件的窗组件和具有通风部分的安全构件
公开(公告)号：US08661734B2
公开(公告)日：2014-03-04
申请号：US12294705
申请日：2007-03-28
申请人： Ian Kernaghan , Kevin Gorman
发明人： Ian Kernaghan , Kevin Gorman
IPC分类号： E06B3/44
CPC分类号： E06B3/4618 , E06B5/003 , E06B9/04 , E06B9/52 , E06B2009/527 , Y10T24/44017
摘要： A window assembly (30) comprising a frame (36) in which are received sliding and security members. The security member has ventilating and non-ventilating parts (40, 32), with the sliding member (34) being slidably moveable over the security member between a first position in which air may pass through the ventilating part (40) so as to ventilate the room in which the window assembly (30) is located, and a second position in which no such ventilation can occur. The ventilating part 40 may comprise a grille, perforated sheet, lattice arrangement or the like.
摘要翻译：包括框架（36）的窗户组件（30），其中容纳有滑动和安全构件。安全部件具有通风和非通风部件（40,32），其中滑动部件（34）能够在第一位置和第二位置之间滑动地移动到安全部件上，空气可以通过通风部分（40）通风窗组件（30）所在的房间以及不会发生这种通风的第二位置。通风部40可以包括格栅，穿孔板，格子布置等。

8. 发明申请

US20100180504A1 Window Assembly 有权
标题翻译：窗户装配
公开(公告)号：US20100180504A1
公开(公告)日：2010-07-22
申请号：US12294705
申请日：2007-03-28
申请人： Ian Kernaghan , Kevin Gorman
发明人： Ian Kernaghan , Kevin Gorman
IPC分类号： E06B3/42 , E06B9/01 , E06B7/16 , A44B99/00 , G05B19/02 , H01H23/00
CPC分类号： E06B3/4618 , E06B5/003 , E06B9/04 , E06B9/52 , E06B2009/527 , Y10T24/44017
摘要： A window assembly (30) comprising a frame (36) in which are received sliding and security members. The security member has ventilating and non-ventilating parts (40, 32), with the sliding member (34) being slidably moveable over the security member between a first position in which air may pass through the ventilating part (40) so as to ventilate the room in which the window assembly (30) is located, and a second position in which no such ventilation can occur. The ventilating part 40 may comprise a grille, perforated sheet, lattice arrangement or the like.
摘要翻译：包括框架（36）的窗户组件（30），其中容纳有滑动和安全构件。安全部件具有通风和非通风部件（40,32），其中滑动部件（34）能够在第一位置和第二位置之间滑动地移动到安全部件上，空气可以通过通风部分（40）通风窗组件（30）所在的房间以及不会发生这种通风的第二位置。通风部40可以包括格栅，穿孔板，格子布置等。

9. 发明申请

US20070177425A1 A METHOD AND APPARATUS FOR REPAIRING EMBEDDED MEMORY IN AN INTEGRATED CIRCUIT 失效
标题翻译：一种用于在集成电路中修复嵌入式存储器的方法和装置
公开(公告)号：US20070177425A1
公开(公告)日：2007-08-02
申请号：US11275827
申请日：2006-01-31
申请人： Kevin Gorman
发明人： Kevin Gorman
IPC分类号： G11C16/06
CPC分类号： G11C29/48 , G11C29/18 , G11C29/36 , G11C29/38 , G11C29/4401 , G11C29/56004 , G11C29/802
摘要： A method and apparatus for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to Built-In Test (BIST) logic in combination with a Built-In Redundancy Analyzer (BIRA) to replace the defective memory element with a redundant element.
摘要翻译：一种用于校正被存储器控制器识别为有缺陷的嵌入式存储器的方法和装置。有缺陷的存储器的地址由存储器控制器提供给内置测试（BIST）逻辑与内置冗余分析器（BIRA）的组合，以用冗余元件替换有缺陷的存储器元件。

10. 发明申请

US20060259840A1 SELF-TEST CIRCUITRY TO DETERMINE MINIMUM OPERATING VOLTAGE 审中-公开
标题翻译：自检电路确定最小工作电压
公开(公告)号：US20060259840A1
公开(公告)日：2006-11-16
申请号：US10908452
申请日：2005-05-12
申请人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
发明人： Wagdi Abadeer , George Braceras , Anthony Bonaccio , Kevin Gorman
IPC分类号： G01R31/28
CPC分类号： G01R31/3004
摘要： A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).
摘要翻译：用于确定由于性能/功率要求而导致的最小工作电压的解决方案对于广泛的实际应用是有效的。该解决方案包括测试流程方法，用于在应用条件下动态降低功耗，同时通过BIST电路保持应用性能。另外提供了一种测试流程方法，用于在仍然足以维护数据/状态信息的应用条件下将功耗动态地降低到最低可能待机/极低功率水平。一种可能的应用是用于控制对ASIC（专用集成电路）上的一组特定电路的电压供应。这些电路分组在一个电压岛中，在那里它们将接收可以与同一芯片正在接收的其它电路的电压供给不同的电压源。相同的解决方案可以应用于微处理器的一部分（例如，高速缓存逻辑控制）。

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