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1. 发明授权

US07071101B1 Sacrificial TiN arc layer for increased pad etch throughput 有权
标题翻译：牺牲TiN电弧层，用于增加焊盘蚀刻吞吐量
公开(公告)号：US07071101B1
公开(公告)日：2006-07-04
申请号：US09208325
申请日：1998-12-09
申请人： Jeffrey A. Shields , Kelwin Ko
发明人： Jeffrey A. Shields , Kelwin Ko
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31138 , H01L21/32136
摘要： A method of manufacturing a semiconductor device wherein a final layer of metal is formed on a layer of interlayer dielectric, forming a layer of TiN on the final layer of metal, forming a layer of photoresist on the layer of TiN, patterning and developing the layer of photoresist exposing portions of the final metal layer, and etching the exposed portions of the final metal layer forming metal structures. The layer of photoresist and layer of TiN are removed. A blanket layer of interlayer dielectric is formed on the surface of the semiconductor device. A second layer of photoresist is formed on the blanket layer of interlayer dielectric. The second layer of photoresist is patterned and developed exposing portions of the interlayer dielectric overlying the metal structures. The exposed portions of the interlayer dielectric are etched down to the surface of the metal structures.
摘要翻译：一种制造半导体器件的方法，其中在层间电介质层上形成最终的金属层，在金属的最终层上形成TiN层，在TiN层上形成光致抗蚀剂层，图案化和显影层的光致抗蚀剂暴露最终金属层的部分，并蚀刻最终金属层形成金属结构的暴露部分。去除光致抗蚀剂层和TiN层。在半导体器件的表面上形成层间绝缘层的覆盖层。在层间电介质的覆盖层上形成第二层光致抗蚀剂。将第二层光致抗蚀剂图案化和显影，使覆盖金属结构的层间电介质的部分暴露。层间电介质的暴露部分被蚀刻到金属结构的表面。

2. 发明授权

US6130169A Efficient in-situ resist strip process for heavy polymer metal etch 有权
标题翻译：用于重聚合物金属蚀刻的高效原位抗蚀剂剥离工艺
公开(公告)号：US6130169A
公开(公告)日：2000-10-10
申请号：US316491
申请日：1999-05-21
申请人： Jeffrey A. Shields , King Wai Kelwin Ko , Leobardo Mercado
发明人： Jeffrey A. Shields , King Wai Kelwin Ko , Leobardo Mercado
IPC分类号： G03F7/42 , H01L21/311 , H01L21/00
CPC分类号： G03F7/427 , H01L21/31138
摘要： The inventive method allows for a more complete stripping of photoresist and sidewall polymer in the production of semiconductor devices using a four step process in a plasma stripper. The first step uses CF.sub.4, O.sub.2, and H.sub.2 O as etchant gases in a downstream quartz (DSQ) chamber at a low pressure, which are ionized by radio waves for a period of between 5 and 20 seconds. The second step discontinues the radio waves, while continuing the flow of etchant gases and heating the semiconductor. The third step only provides H.sub.2 O vapor to the DSQ chamber. The fourth step provides both O.sub.2 and H.sub.2 O as etchant gases ionized by radio waves to remove the remaining resist.
摘要翻译：本发明的方法允许在制造半导体器件中使用等离子体剥离器中的四步法来更完整地剥离光致抗蚀剂和侧壁聚合物。第一步使用CF4，O2和H2O作为低压下游石英（DSQ）室中的蚀刻气体，这些气体通过无线电波电离5到20秒的时间。第二步停止无线电波，同时继续蚀刻气体的流动并加热半导体。第三步仅将H2O蒸汽提供给DSQ室。第四步提供O2和H2O，因为蚀刻剂气体通过无线电波电离以除去剩余的抗蚀剂。

3. 发明申请

US20090163018A1 Method to prevent alloy formation when forming layered metal oxides by metal oxidation 有权
标题翻译：通过金属氧化形成层状金属氧化物时防止合金形成的方法
公开(公告)号：US20090163018A1
公开(公告)日：2009-06-25
申请号：US12004124
申请日：2007-12-20
申请人： Steven Avanzino , Jeffrey A. Shields , Joffre Bernard , Suzette K. Pangrle
发明人： Steven Avanzino , Jeffrey A. Shields , Joffre Bernard , Suzette K. Pangrle
IPC分类号： H01L21/4763
CPC分类号： H01L21/31683 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： The present method of fabricating a resistive memory device includes the steps of providing a first electrode, oxidizing a portion of the first electrode with an oxidizing agent, providing a metal body on the oxidized portion of the first electrode, oxidizing the entire metal body with an oxidizing agent, and providing a second electrode on the oxidized metal body.
摘要翻译：制造电阻式存储器件的本方法包括以下步骤：提供第一电极，用氧化剂氧化第一电极的一部分，在第一电极的氧化部分上提供金属体，用金属体氧化整个金属体氧化剂，并在氧化的金属体上提供第二电极。

4. 发明授权

US07091088B1 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing 有权
标题翻译：用于减少BEOL处理中的存储器件中的电荷存储层的UV诱导的充电的UV阻挡蚀刻停止层
公开(公告)号：US07091088B1
公开(公告)日：2006-08-15
申请号：US10861437
申请日：2004-06-03
申请人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
发明人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
IPC分类号： H01L21/336
CPC分类号： H01L23/53295 , H01L21/76829 , H01L27/115 , H01L27/11568 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷捕获电介质闪存单元上沉积至少一个UV保护层; 在所述至少一个UV保护层上形成至少一层; 以及蚀刻所述至少一个层以在其中形成具有选择性地停留在所述至少一个UV保护层下方的层上的蚀刻剂物质的开口，其中所述UV保护层包括基本上不透紫外线的材料。

5. 发明授权

US06794298B2 CF4+H2O plasma ashing for reduction of contact/via resistance 失效
标题翻译： CF4 + H2O等离子体灰化还原接触/通孔电阻
公开(公告)号：US06794298B2
公开(公告)日：2004-09-21
申请号：US09498336
申请日：2000-02-04
申请人： Jeffrey A. Shields , Lu You , Mohammad R. Rakhshandehroo
发明人： Jeffrey A. Shields , Lu You , Mohammad R. Rakhshandehroo
IPC分类号： H01L2120
CPC分类号： H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814
摘要： The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by employing a plasma containing CF4+H2O to remove the photoresist mask and cleaning the contact/via opening after anisotropic etching. The CF4+H2O plasma also enables rapid photoresist stripping at a rate of about 10 to about 20 KÅ/min. Embodiments include photoresist stripping and cleaning the contact/via opening with a CF4+H2O plasma to prevent reduction of the number of Si—H bonds of an as-deposited HSQ layer below about 70%.
摘要翻译：通过使用含有CF 4 + H 2 O的等离子体去除光致抗蚀剂掩模并清洁接触/通孔，显着降低或防止沉积的低介电常数层间电介质和间隙填充层（例如HSQ层）在形成接触/通孔期间的劣化各向异性蚀刻后。 CF4 + H2O等离子体还可以以约10至约20K埃/分钟的速率快速地进行光致抗蚀剂剥离。实施方案包括光致抗蚀剂剥离和用CF 4 + H 2 O等离子体清洁接触/通孔开口，以防止沉积的HSQ层的Si-H键的数量降低到约70％以下。

6. 发明授权

US06774432B1 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL 有权
标题翻译：紫外线阻挡层，用于降低BEOL中SONOS双位闪存器件的UV感应充电
公开(公告)号：US06774432B1
公开(公告)日：2004-08-10
申请号：US10358589
申请日：2003-02-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L29792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 SONOS闪存设备，包括SONOS闪存单元; 以及至少一个UV保护层，其中UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括基本上不透紫外线的接触盖层。

7. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

8. 发明授权

US06551923B1 Dual width contact for charge gain reduction 失效
标题翻译：双宽度接点用于减少电荷增益
公开(公告)号：US06551923B1
公开(公告)日：2003-04-22
申请号：US09430845
申请日：1999-11-01
申请人： Jeffrey A. Shields , Bharath Rangarajan
发明人： Jeffrey A. Shields , Bharath Rangarajan
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829
摘要： A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, creating a second aperture in the first insulating layer below the first aperture, and filling the first and second apertures with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.
摘要翻译：本文公开了在集成电路中形成接触的方法。该方法包括在包括第一和第二栅极结构的半导体衬底之上提供第一绝缘层，在第一绝缘层上提供蚀刻停止层，在蚀刻停止层上方提供第二绝缘层，在第二绝缘层中形成第一孔在第一和第二栅极结构之间，在第一孔下面的第一绝缘层中形成第二孔，并用导电材料填充第一和第二孔以形成接触。第一孔具有第一孔径宽度并延伸到蚀刻停止层。第二孔径具有小于第一孔径宽度的第二孔径宽度。

9. 发明授权

US06500768B1 Method for selective removal of ONO layer 有权
标题翻译：选择性去除ONO层的方法
公开(公告)号：US06500768B1
公开(公告)日：2002-12-31
申请号：US09699531
申请日：2000-10-30
申请人： Jeffrey A. Shields , Jiahua Huang , Jean Yee-Mei Yang
发明人： Jeffrey A. Shields , Jiahua Huang , Jean Yee-Mei Yang
IPC分类号： H01L21302
CPC分类号： H01L21/31116
摘要： A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.
摘要翻译：一种制造半导体器件的方法，该方法包括提供其上具有氧化物 - 氮化物 - 氧化物层的半导体衬底和覆盖氧化物 - 氮化物 - 氧化物层的图案化抗蚀剂层，其中氧化物 - 氮化物 - 氧化物层包括第一氧化物层，覆盖第一氧化物层的氮化物层和覆盖氮化物层的第二氧化物层。该方法还包括：在氧化物 - 氮化物 - 氧化物层上进行各向同性蚀刻以去除氧化物 - 氮化物 - 氧化物层的一部分。

10. 发明授权

US06261956B1 Modified product mask for bridging detection 失效
标题翻译：用于桥接检测的修改产品掩码
公开(公告)号：US06261956B1
公开(公告)日：2001-07-17
申请号：US09398207
申请日：1999-09-17
申请人： Jeffrey A. Shields
发明人： Jeffrey A. Shields
IPC分类号： H01L21302
CPC分类号： H01L22/34
摘要： A bridging test structure is formed by using a modified product mask that has similar loading characteristics as an actual product mask. The modified product mask is used for devices having somewhat uniform structures, such as memory cell arrays with vertical and horizontal conductive lines. Even ones of the vertical lines are connected together by using a first horizontal line that is connected to a first test pad. Odd ones of the vertical lines are connected together by using a second horizontal line that is connected to a second test pad. Current is applied to one of the test pads to determine if that current is detected at the other test pad, and if so, a bridging problem is determined to exist.
摘要翻译：通过使用具有与实际产品掩模相似的负载特性的改进产品掩模形成桥接测试结构。改进的产品掩模用于具有稍微均匀结构的器件，例如具有垂直和水平导线的存储单元阵列。通过使用连接到第一测试垫的第一水平线将偶数垂直线连接在一起。通过使用连接到第二测试垫的第二水平线将垂直线中的奇数个连接在一起。将电流施加到一个测试焊盘，以确定在另一个测试焊盘是否检测到该电流，如果是，则确定桥接问题存在。

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