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    • 3. 发明授权
    • Structure of semiconductor device with sinker contact region
    • 具有沉降片接触区域的半导体器件的结构
    • US07164186B2
    • 2007-01-16
    • US10939221
    • 2004-09-10
    • Angelo PintoJeffrey A. BabcockMichael SchoberScott G. BalsterChristoph Dirnecker
    • Angelo PintoJeffrey A. BabcockMichael SchoberScott G. BalsterChristoph Dirnecker
    • H01L29/70
    • H01L29/66272H01L29/41708
    • A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
    • 半导体器件的制造方法包括形成半导体衬底的掩埋层。 在掩埋层的至少一部分附近形成有源区。 在掩埋层的至少一部分附近形成第一隔离结构。 在活性区域的至少一部分附近形成第二隔离结构。 在活性区域的至少一部分附近形成基底层。 在基底层的至少一部分附近形成电介质层,然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。 发射极结构形成在发射极接触位置。 形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。 沉降片接触区域具有第一深度。 该方法还可以包括形成栅极结构。 形成栅极结构包括蚀刻沉降片接触区域,从而将沉降片接触区域的第一深度增加到第二深度。
    • 4. 发明授权
    • Method of manufacturing a zero mask high density metal/insulator/metal capacitor
    • 制造零掩模高密度金属/绝缘体/金属电容器的方法
    • US06391707B1
    • 2002-05-21
    • US09849299
    • 2001-05-04
    • Christoph DirneckerJeffrey A. BabcockMichael SchoberScott G. BalsterAngelo Pinto
    • Christoph DirneckerJeffrey A. BabcockMichael SchoberScott G. BalsterAngelo Pinto
    • H01L218242
    • H01L28/60H01L21/3212H01L23/5223H01L28/90H01L29/66181H01L2924/0002H01L2924/00
    • The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor. The resulting capacitor has a relatively large effective electrode surface area (which is a function of the depth of the via) for a given lateral dimension.
    • 本发明涉及形成具有相对电容的集成电路MIM电容器的结构和方法,而不需要额外的掩模步骤。 形成集成电路电容器的方法包括以下步骤:在相同的图案化工艺期间在电绝缘层中形成标准通孔和一个或多个放大通孔,然后形成填充标准通孔的导电第一电极层并覆盖放大的通孔 保形方式。 然后在导电的第一电极层上形成电介质层。 接下来,在电介质层上形成导电的第二电极层,覆盖和/或填充放大的通孔。 然后执行步骤以使第二电极层,电介质层和第一电极层平坦化,以限定电容器的电极。 对于给定的横向尺寸,所得的电容器具有相对较大的有效电极表面积(其是通孔的深度的函数)。
    • 5. 发明授权
    • Method for manufacturing a semiconductor device with sinker contact region
    • 制造具有沉降片接触区域的半导体器件的方法
    • US06806159B2
    • 2004-10-19
    • US10262211
    • 2002-09-30
    • Angelo PintoJeffrey A. BabcockMichael SchoberScott G. BalsterChristoph Dirnecker
    • Angelo PintoJeffrey A. BabcockMichael SchoberScott G. BalsterChristoph Dirnecker
    • H01L21331
    • H01L29/66272H01L29/41708
    • A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
    • 半导体器件的制造方法包括形成半导体衬底的掩埋层。 在掩埋层的至少一部分附近形成有源区。 在掩埋层的至少一部分附近形成第一隔离结构。 在活性区域的至少一部分附近形成第二隔离结构。 在活性区域的至少一部分附近形成基底层。 在基底层的至少一部分附近形成电介质层,然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。 发射极结构形成在发射极接触位置。 形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。 沉降片接触区域具有第一深度。 该方法还可以包括形成栅极结构。 形成栅极结构包括蚀刻沉降片接触区域,从而将沉降片接触区域的第一深度增加到第二深度。
    • 6. 发明授权
    • Control of dopant diffusion from buried layers in bipolar integrated circuits
    • 控制双极集成电路中埋层的掺杂剂扩散
    • US08247300B2
    • 2012-08-21
    • US12627794
    • 2009-11-30
    • Jeffrey A. BabcockAngelo PintoManfred SchiekoferScott G. BalsterGregory E. HowardAlfred Hausler
    • Jeffrey A. BabcockAngelo PintoManfred SchiekoferScott G. BalsterGregory E. HowardAlfred Hausler
    • H01L21/8222
    • H01L29/66265H01L21/82285H01L29/66242H01L29/7317H01L29/7378
    • An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
    • 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管(30,50,60),每个具有一个埋设集电极区域(26')。 含碳扩散阻挡层(28c)设置在掩埋集电极区域(26')之上,以阻止掺杂剂从掩埋的集电极区域(26')扩散到上覆的外延层(28)中。 扩散阻挡层(28c)可以通过将碳源引入上覆层(28)的外延层中,或通过离子注入形成。 在碳或SiGeC的离子注入的情况下,可以使用掩模(52,62)来限定待接收碳的掩埋收集器区域(26')的位置; 例如,最终的集电极触点(33,44c)下面的部分可以从碳注入掩模,使得来自掩埋的集电极区域(26')的掺杂剂可向上扩散以满足触点(33)。 还公开了包括扩散阻挡层(28)的MOS晶体管(70,80)。
    • 8. 发明申请
    • CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS
    • 双极性集成电路中碲化镓的掺杂扩散控制
    • US20100279481A1
    • 2010-11-04
    • US12627794
    • 2009-11-30
    • Jeffrey A. BabcockAngelo PintoManfred SchiekoferScott G. BalsterGregory E. HowardAlfred Hausler
    • Jeffrey A. BabcockAngelo PintoManfred SchiekoferScott G. BalsterGregory E. HowardAlfred Hausler
    • H01L21/331
    • H01L29/66265H01L21/82285H01L29/66242H01L29/7317H01L29/7378
    • An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
    • 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管(30,50,60),每个具有一个埋设集电极区域(26')。 含碳扩散阻挡层(28c)设置在掩埋集电极区域(26')之上,以阻止掺杂剂从掩埋的集电极区域(26')扩散到上覆的外延层(28)中。 扩散阻挡层(28c)可以通过将碳源引入上覆层(28)的外延层中,或通过离子注入形成。 在碳或SiGeC的离子注入的情况下,可以使用掩模(52,62)来限定待接收碳的掩埋收集器区域(26')的位置; 例如,最终的集电极触点(33,44c)下面的部分可以从碳注入掩模,使得来自掩埋的集电极区域(26')的掺杂剂可向上扩散以满足触点(33)。 还公开了包括扩散阻挡层(28)的MOS晶体管(70,80)。